|Title:||Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation||Authors:||Cervero, T.
De La Torre, E.
Callicó, G. M.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||MB-level parallelism SVC H.264/AVC FPGA Deblocking filter||Issue Date:||2011||Publisher:||0277-786X||Journal:||Proceedings of SPIE - The International Society for Optical Engineering||Conference:||Conference on VLSI Circuits and Systems V||Abstract:||One of the most computational intensive tasks in recent video encoders and decoders is the deblocking filter. Its computational complexity is considerable, and it might take more than 30% of the total computational cost of the decoder execution. Nowadays, some of its limiting factors for reaching real-time capabilities are mainly related with memory and speed. Trying to deal with these factors, this paper proposes a novel Deblocking filter architecture which supports all filtering modes available in both the H.264/AVC and Scalable Video Coding (SVC) standards. It has been implemented in a hardware scalable architecture, which benefits of the parallelism and adaptability of the algorithm and which can be adapted dynamically in FPGAs.Regarding to the parallelism, this architecture mapping is capable of respecting data dependencies among MBs while several functional units (FU) are filtering data in parallel. Regarding scalability, the architecture is flexible enough for adapting its performance to the diverse environment demands. This fact is possible by increasing or decreasing the number of FUs, like in a systolic array. In this sense, this paper will present a composition between the FU proposed against the state-of-the art work.||URI:||http://hdl.handle.net/10553/44409||ISBN:||9780819486561||ISSN:||0277-786X||DOI:||10.1117/12.887951||Source:||Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 8067 (80670K)|
|Appears in Collections:||Actas de congresos|
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