Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/44406
DC FieldValueLanguage
dc.contributor.authorCervero, T.en_US
dc.contributor.authorLopez, S.en_US
dc.contributor.authorSarmiento, R.en_US
dc.contributor.authorFrangieh, T.en_US
dc.contributor.authorAthanas, P.en_US
dc.date.accessioned2018-11-21T22:47:59Z-
dc.date.available2018-11-21T22:47:59Z-
dc.date.issued2011en_US
dc.identifier.isbn9780769545516en_US
dc.identifier.urihttp://hdl.handle.net/10553/44406-
dc.description.abstractFPGAs are well-suited for applications that need to adjust the composition of computational structures over the lifetime of the application. While the underlying hardware framework for supporting run-time reconfiguration has existed for years, there have been negligibly few FPGA applications that have benefited from this. This is likely not an issue with FPGA architectures, yet it is more likely a formulation problem due to a highly restrictive model for reconfiguration provided by the vendors. This paper introduces a new paradigm in reconfigurable computing, where multiple designs may dynamically compete for resources in the same die. The way to afford this challenge is taking advantage of the benefits of the scalable and adaptable designs, since they achieve a balance between performance and flexibility. Thus, this paper proposes two alternative models for the assembly of computational structures that are conducive to autonomous self-assembled embedded systems, because of their high level of adaptability. To illustrate this new scenario, an example is examined that is based on two competing video image processing tasks.en_US
dc.languagespaen_US
dc.relation.ispartofProceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011en_US
dc.sourceProceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 (6128612), p. 410-415en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherField programmable gate arrays , Computational modeling , Assembly , Adaptation models , Libraries , Kernel , Shape , Dynamic Reconfiguration , Field-Programmable , Gate Array , Modular-Assembly , Tile-Model Assemblyen_US
dc.titleScalable models for autonomous self-assembled reconfigurable systemsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.typeConferenceObjectes
dc.relation.conference2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011
dc.identifier.doi10.1109/ReConFig.2011.81
dc.identifier.scopus84856869350-
dc.contributor.authorscopusid34978225000-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid35609452100-
dc.contributor.authorscopusid24779225400-
dc.contributor.authorscopusid6701824326-
dc.description.lastpage415-
dc.identifier.issue6128612-
dc.description.firstpage410-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.date.coverdateDiciembre 2011
dc.identifier.conferenceidevents121427
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate30-11-2011-
crisitem.event.eventsenddate02-12-2011-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameCervero García, Teresa Gloria-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
Appears in Collections:Actas de congresos
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