Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/44000
Title: Design methodology of an equalizer for unipolar non return to zero binary signals in the presence of additive white Gaussian Noise using a time delay neural network on a field programmable gate array
Authors: Pérez Suárez, Santiago T. 
Travieso González, Carlos M. 
Alonso Hernández, Jesús B. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: equalizer; AWGN; neural network; FPGA; floating point; fixed point; Matlab; Simulink; System Generator; ISE
Issue Date: 2013
Publisher: 1424-8220
Journal: Sensors 
Abstract: This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers
URI: http://hdl.handle.net/10553/44000
ISSN: 1424-8220
DOI: 10.3390/s131216829
Source: Sensors (Switzerland)[ISSN 1424-8220],v. 13, p. 16829-16850
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