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Title: A comprehensive analysis of indirect branch prediction
Authors: Santana Jaria, Oliverio Jesús 
Falcón, Ayose
Fernández García, Enrique 
Medina Rodríguez, Pedro 
Ramírez, Alex
Valero, Mateo
UNESCO Clasification: 330406 Arquitectura de ordenadores
Keywords: Microarchitecture
Branch prediction
Branch target buffer
Indirect branch
Multi-stage cascaded predictor
Issue Date: 2002
Publisher: Springer 
Journal: Lecture Notes in Computer Science 
Conference: 4th International Symposium on High Performance Computing, ISHPC 2002 
Abstract: Indirect branch prediction is a performance limiting factor for current computer systems, preventing superscalar processors from exploiting the available ILP. Indirect branches are responsible for 55.7% of mispredictions in our benchmark set, although they only stand for 15.5% of dynamic branches. Moreover, a 10.8% average IPC speedup is achievable by perfectly predicting all indirect branches. The Multi-Stage Cascaded Predictor (MSCP) is a mechanism proposed for improving indirect branch prediction. In this paper, we show that a MSCP can replace a BTB and accurately predict the target address of both indirect and non-indirect branches. We do a detailed analysis of MSCP behavior and evaluate it in a realistic setup, showing that a 5.7% average IPC speedup is achievable.
ISBN: 978-3-540-43674-4
ISSN: 0302-9743
DOI: 10.1007/3-540-47847-7_13
Source: Zima H.P., Joe K., Sato M., Seo Y., Shimasaki M. (eds) High Performance Computing. ISHPC 2002. Lecture Notes in Computer Science, vol 2327. Springer, Berlin, Heidelberg
Appears in Collections:Actas de congresos
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