Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/35376
DC FieldValueLanguage
dc.contributor.authorMadroñal, D.en_US
dc.contributor.authorLazcano, R.en_US
dc.contributor.authorSalvador, R.en_US
dc.contributor.authorFabelo, H.en_US
dc.contributor.authorOrtega, S.en_US
dc.contributor.authorCallico, G. M.en_US
dc.contributor.authorJuarez, E.en_US
dc.contributor.authorSanz, C.en_US
dc.date.accessioned2018-04-13T13:19:19Z-
dc.date.available2018-04-13T13:19:19Z-
dc.date.issued2017en_US
dc.identifier.issn1383-7621en_US
dc.identifier.urihttp://hdl.handle.net/10553/35376-
dc.description.abstractThis paper presents a study of the design space of a Support Vector Machine (SVM) classifier with a linear kernel running on a manycore MPPA (Massively Parallel Processor Array) platform. This architecture gathers 256 cores distributed in 16 clusters working in parallel. This study aims at implementing a real-time hyperspectral SVM classifier, where real-time is defined as the time required to capture a hyperspectral image. To do so, two aspects of the SVM classifier have been analyzed: the classification algorithm and the system parallelization. On the one hand, concerning the classification algorithm, first, the classification model has been optimized to fit into the MPPA structure and, secondly, a probability estimation stage has been included to refine the classification results. On the other hand, the system parallelization has been divided into two levels: first, the parallelism of the classification has been exploited taking advantage of the pixel-wise classification methodology supported by the SVM algorithm and, secondly, a double-buffer communication procedure has been implemented to parallelize the image transmission and the cluster classification stages. Experimenting with medical images, an average speedup of 9 has been obtained using a single-cluster and double-buffer implementation with 16 cores working in parallel. As a result, a system whose processing time linearly grows with the number of pixels composing the scene has been implemented. Specifically, only 3 mu s are required to process each pixel within the captured scene independently from the spatial resolution of the image.en_US
dc.languageengen_US
dc.relation.ispartofJournal of Systems Architecture
dc.sourceJournal of Systems Architecture[ISSN 1383-7621],v. 80, p. 30-40en_US
dc.subject33 Ciencias tecnológicasen_US
dc.subject.otherSupport Vector Machineen_US
dc.subject.otherHyperspectral imagingen_US
dc.subject.otherMassively parallel processingen_US
dc.subject.otherReal-time processingen_US
dc.subject.otherEnergy consumption awarenessen_US
dc.subject.otherEmbedded systemen_US
dc.titleSVM-based real-time hyperspectral image classifier on a manycore architectureen_US
dc.typeinfo:eu-repo/semantics/Articlees
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticlees
dc.relation.conferenceConference on Design and Architectures for Signal and Image Processing (DASIP)
dc.identifier.doi10.1016/j.sysarc.2017.08.002
dc.identifier.scopus85028765915
dc.identifier.isi000413883100003-
dc.contributor.authorscopusid57192829417
dc.contributor.authorscopusid57192839213
dc.contributor.authorscopusid23005852100
dc.contributor.authorscopusid56405568500
dc.contributor.authorscopusid57189334144
dc.contributor.authorscopusid56006321500
dc.contributor.authorscopusid36447485600
dc.contributor.authorscopusid7006751614
dc.identifier.eissn1873-6165-
dc.description.lastpage40-
dc.description.firstpage30-
dc.relation.volume80-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid3360488
dc.contributor.daisngid3634522
dc.contributor.daisngid1888017
dc.contributor.daisngid2096372
dc.contributor.daisngid1812298
dc.contributor.daisngid506422
dc.contributor.daisngid693458
dc.contributor.daisngid384271
dc.contributor.wosstandardWOS:Madronal, D
dc.contributor.wosstandardWOS:Lazcano, R
dc.contributor.wosstandardWOS:Salvador, R
dc.contributor.wosstandardWOS:Fabelo, H
dc.contributor.wosstandardWOS:Ortega, S
dc.contributor.wosstandardWOS:Callico, GM
dc.contributor.wosstandardWOS:Juarez, E
dc.contributor.wosstandardWOS:Sanz, C
dc.date.coverdateOctubre 2017
dc.identifier.conferenceidevents121055
dc.identifier.ulpgces
dc.description.sjr0,255
dc.description.jcr0,913
dc.description.sjrqQ3
dc.description.jcrqQ3
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-9794-490X-
crisitem.author.orcid0000-0002-7519-954X-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameFabelo Gómez, Himar Antonio-
crisitem.author.fullNameOrtega Sarmiento, Samuel-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
crisitem.event.eventsstartdate12-10-2016-
crisitem.event.eventsenddate14-10-2016-
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