Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/35376
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Madroñal, D. | en_US |
dc.contributor.author | Lazcano, R. | en_US |
dc.contributor.author | Salvador, R. | en_US |
dc.contributor.author | Fabelo, H. | en_US |
dc.contributor.author | Ortega, S. | en_US |
dc.contributor.author | Callico, G. M. | en_US |
dc.contributor.author | Juarez, E. | en_US |
dc.contributor.author | Sanz, C. | en_US |
dc.date.accessioned | 2018-04-13T13:19:19Z | - |
dc.date.available | 2018-04-13T13:19:19Z | - |
dc.date.issued | 2017 | en_US |
dc.identifier.issn | 1383-7621 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/35376 | - |
dc.description.abstract | This paper presents a study of the design space of a Support Vector Machine (SVM) classifier with a linear kernel running on a manycore MPPA (Massively Parallel Processor Array) platform. This architecture gathers 256 cores distributed in 16 clusters working in parallel. This study aims at implementing a real-time hyperspectral SVM classifier, where real-time is defined as the time required to capture a hyperspectral image. To do so, two aspects of the SVM classifier have been analyzed: the classification algorithm and the system parallelization. On the one hand, concerning the classification algorithm, first, the classification model has been optimized to fit into the MPPA structure and, secondly, a probability estimation stage has been included to refine the classification results. On the other hand, the system parallelization has been divided into two levels: first, the parallelism of the classification has been exploited taking advantage of the pixel-wise classification methodology supported by the SVM algorithm and, secondly, a double-buffer communication procedure has been implemented to parallelize the image transmission and the cluster classification stages. Experimenting with medical images, an average speedup of 9 has been obtained using a single-cluster and double-buffer implementation with 16 cores working in parallel. As a result, a system whose processing time linearly grows with the number of pixels composing the scene has been implemented. Specifically, only 3 mu s are required to process each pixel within the captured scene independently from the spatial resolution of the image. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Journal of Systems Architecture | |
dc.source | Journal of Systems Architecture[ISSN 1383-7621],v. 80, p. 30-40 | en_US |
dc.subject | 33 Ciencias tecnológicas | en_US |
dc.subject.other | Support Vector Machine | en_US |
dc.subject.other | Hyperspectral imaging | en_US |
dc.subject.other | Massively parallel processing | en_US |
dc.subject.other | Real-time processing | en_US |
dc.subject.other | Energy consumption awareness | en_US |
dc.subject.other | Embedded system | en_US |
dc.title | SVM-based real-time hyperspectral image classifier on a manycore architecture | en_US |
dc.type | info:eu-repo/semantics/Article | en_US |
dc.type | info:eu-repo/semantics/Article | es |
dc.type | Article | es |
dc.relation.conference | Conference on Design and Architectures for Signal and Image Processing (DASIP) | |
dc.identifier.doi | 10.1016/j.sysarc.2017.08.002 | |
dc.identifier.scopus | 85028765915 | |
dc.identifier.isi | 000413883100003 | - |
dc.contributor.authorscopusid | 57192829417 | |
dc.contributor.authorscopusid | 57192839213 | |
dc.contributor.authorscopusid | 23005852100 | |
dc.contributor.authorscopusid | 56405568500 | |
dc.contributor.authorscopusid | 57189334144 | |
dc.contributor.authorscopusid | 56006321500 | |
dc.contributor.authorscopusid | 36447485600 | |
dc.contributor.authorscopusid | 7006751614 | |
dc.identifier.eissn | 1873-6165 | - |
dc.description.lastpage | 40 | - |
dc.description.firstpage | 30 | - |
dc.relation.volume | 80 | - |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Artículo | en_US |
dc.contributor.daisngid | 3360488 | |
dc.contributor.daisngid | 3634522 | |
dc.contributor.daisngid | 1888017 | |
dc.contributor.daisngid | 2096372 | |
dc.contributor.daisngid | 1812298 | |
dc.contributor.daisngid | 506422 | |
dc.contributor.daisngid | 693458 | |
dc.contributor.daisngid | 384271 | |
dc.contributor.wosstandard | WOS:Madronal, D | |
dc.contributor.wosstandard | WOS:Lazcano, R | |
dc.contributor.wosstandard | WOS:Salvador, R | |
dc.contributor.wosstandard | WOS:Fabelo, H | |
dc.contributor.wosstandard | WOS:Ortega, S | |
dc.contributor.wosstandard | WOS:Callico, GM | |
dc.contributor.wosstandard | WOS:Juarez, E | |
dc.contributor.wosstandard | WOS:Sanz, C | |
dc.date.coverdate | Octubre 2017 | |
dc.identifier.conferenceid | events121055 | |
dc.identifier.ulpgc | Sí | es |
dc.description.sjr | 0,255 | |
dc.description.jcr | 0,913 | |
dc.description.sjrq | Q3 | |
dc.description.jcrq | Q3 | |
dc.description.scie | SCIE | |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-9794-490X | - |
crisitem.author.orcid | 0000-0002-7519-954X | - |
crisitem.author.orcid | 0000-0002-3784-5504 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Fabelo Gómez, Himar Antonio | - |
crisitem.author.fullName | Ortega Sarmiento,Samuel | - |
crisitem.author.fullName | Marrero Callicó, Gustavo Iván | - |
crisitem.event.eventsstartdate | 12-10-2016 | - |
crisitem.event.eventsenddate | 14-10-2016 | - |
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