FPGA Implementation of a Low-Complexity H.264 Output Coding Stage for Space Missions

Abstract

Recent space missions increasingly use video sensors for enhanced observation, real-Time monitoring and decision making. Video cameras generate large data volumes that are challenging due to the limited transmission bandwidths, hardware and power available on space systems. On-board video compression is essential to reduce data size while limiting quality losses, thus enabling efficient transmission and storage. This works presents a low-complexity H. 264 compliant output subsystem. This system is able to autonomously generate a correct compressed bitstream. An area-optimized CAVLC entropy coding stage is included in the proposed architecture. Results demonstrate that the entropy coder is able to manage throughputs of up to 0.78 Macroblocks/s while keeping resource utilization at minimal levels (0.63 \% LUTs, 0.28% FFs, no BRAMs) on a Xilinx Kintex UltraScale XCKU040 FPGA.