Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/129249
Title: CCSDS121-based High-Performance Hardware Architecture for Real-Time Data Compression
Authors: Torres Fau, Samuel 
Sanchez, Antonio J.
Barrios,Yubal 
Sarmiento, Roberto 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Data Handling
High-Performance On-Board Processing
Real-Time Data Compression
Space Data Compression
Issue Date: 2023
Journal: Proceedings Of The 2023 European Data Handling And Data Processing Conference For Space, Edhpc 2023
Conference: 2023 European Data Handling and Data Processing Conference for Space, EDHPC 2023 
Abstract: Imaging sensors embarked on Earth Observation satellites are increasing their acquisition capabilities in terms of resolution. The amount of data collected need to be reduced prior to be sent to ground, because of on-board storage limitations and the constrained downlink bandwidth. This results in the need of implementing compression techniques as part of the data handling system. This work presents a high-performance architecture based on the Consultative Committee for Space Data Systems (CCSDS) 121.0-B-3 data compression standard that is able to process collected data in real-Time and with an associated low area footprint. Starting from the basis of the Hyperspectral Lossless Compressor for space applications (SHyLoC) 3.0 CCSDS-121 IP, a highly parallelized architecture, in which an operation-based control allows the effective coordination of the independent processing pipelines, has been designed and described in VHDL. Results demonstrate that this architecture is able to process data throughputs of up to 7.776 Gbps, consuming only the 11.68% of LUTs on a Xilinx Kintex UltraScale XCKU040 FPGA and without using internal memory resources.
URI: http://hdl.handle.net/10553/129249
ISBN: 9789090379241
DOI: 10.23919/EDHPC59100.2023.10395929
Source: Proceedings of the 2023 European Data Handling and Data Processing Conference for Space, EDHPC 2023[EISSN ], (Enero 2023)
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