Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/128826
Title: Abeto: An automated benchmarking tool to manage heterogeneous IP core databases
Authors: Sánchez Clemente, Antonio José 
Barrios Alfaro,Yubal 
Santos Falcón, Lucana 
Sarmiento Rodríguez, Roberto 
UNESCO Clasification: 120312 Bancos de datos
33 Ciencias tecnológicas
3304 Tecnología de los ordenadores
Keywords: Computer aided engineering
Electronic design automation
Database management
IP cores
System-level design
Issue Date: 2024
Project: ESA IP Cores Automated Benchmarking 
Journal: Microprocessors and Microsystems 
Abstract: System-level design makes use of building blocks, known as soft IP cores, to build complex developments. The usage of these IP cores allows to reduce design and verification time, and also to save costs. However, the use of third-party IP cores tends to present difficulties because of a lack of standardization in their organization, distribution and management, which derive in heterogeneous databases. Most of the time, system developers need to describe some additional code to enable the integration, verification and validation of the IP core, which is not available as part of their distribution. This implies acquiring a deep knowledge of each IP core, often with a large learning curve. In this work Abeto is presented, a new software tool for IP core databases management. It allows to easily integrate and use a heterogeneous group of IP cores, described in VHDL, with a unified set of instructions or commands. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of well-known EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate its performance, mapping results for these IP cores on the novel NanoXplore BRAVE FPGA family are provided.
URI: http://hdl.handle.net/10553/128826
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2023.104987
Source: Microprocessors and Microsystems [ ISSN 0141-9331], v. 104, 104987, (Febrero 2024)
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