Capacitance Characterization of Coupled Transmission Lines Applied to VLSI Interconnections Modelling

Abstract

The calculation of the electrical parameters of tr2uismission linea inside CMOS integrated circuits is presented. It is shown that a commonly used 2-D device simulator, MEDICI, can be employed to compute the electrical péiTEtmeters. In pEurticular, decreóising size dimensions in interconnections mótkes parasitic coupling capsicitcince more hnportant. In this work we propose a set of design rules to reduce the coupling problem in the future developments in VLSI interconnection and their impact on peak crosstalk in 0.18 /xm. In order to estímate crosstalk noise in the signal lines, SPICE simulations have been used.