Error masking with approximate logic circuits using dynamic probability estimations

Abstract

Approximate logic circuits can be used in hardware redundancy approaches to reduce the overheads at the expense of slightly sacrificing robustness. However, a major drawback of existing logic approximation methods lies in the difficulty of estimating the effect of approximations in the total error probability and therefore to identify and select optimal approximation transformations. In this work, we propose an approach to build approximate logic circuits for a given acceptable error target. Using signal probabilities, we can dynamically estimate the probability of error that can be expected when an approximation is taken, use it to iteratively select optimal transformations and keep an estimation of the total error probability in order to stick to a given target. Experimental results show how this approach can be used to generate optimal approximate logic circuits for any particular tradeoff between robustness and area overhead.