Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/114632
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dc.contributor.authorNeris Tomé, Roménen_US
dc.contributor.authorRodriguez Molina, Adrianen_US
dc.contributor.authorGuerra, Raulen_US
dc.contributor.authorLopez, Sebastianen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.date.accessioned2022-05-10T09:08:07Z-
dc.date.available2022-05-10T09:08:07Z-
dc.date.issued2022en_US
dc.identifier.issn1939-1404en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/114632-
dc.description.abstractOver the last years, Convolutional Neural Networks (CNNs) have been widely used in remote sensing applications, such as marine surveillance, traffic management or road networks detection. However, since CNNs have extremely high computation, bandwith and memory requirements, the hardware implementation of a CNN on space-grade devices like FPGAs for the on-board processing of the acquired images has brought many challenges. In fact, FPGAs show great advantages in terms of reconfigurability and performance-power ratio, whichmakes them a suitable election to deploy CNNs, although the computational capabilities of this type of hardware devices available on-board is limited, so implementations have to be carefully planned. In this paper, the authors present their work towards the implementation of an efficient CNN onto a spacegrade FPGA in order to achieve the on-board processing of very-high resolution remotely sensed images as soon as the data are provided by the sensor. All this work has been conducted within the EU-funded VIDEO project. As it will be presented in this paper, the work includes the introduction of a methodology based on the project constraints, the evaluation of different state-of-the-art CNN architectures by means of a new efficiency measurement also proposed in this work, the introduction of a new efficient CNN architecture, and finally, its optimized hardware implementation by means of high-level synthesis tools.en_US
dc.languageengen_US
dc.relationMinisterio de Ciencia e Innovacin (Grant Number: PID2020-116417RB-C42)en_US
dc.relationEuropean Commission (Grant Number: 870485)en_US
dc.relation.ispartofIEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensingen_US
dc.sourceIEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing[ISSN 1939-1404], n. 15, p. 3740-3750en_US
dc.subject220990 Tratamiento digital. Imágenesen_US
dc.subject.otherComputer Architectureen_US
dc.subject.otherConvolutional Neural Networksen_US
dc.subject.otherConvolutional Neural Networksen_US
dc.subject.otherDeep Learningen_US
dc.subject.otherEarthen_US
dc.subject.otherField Programmable Gate Arraysen_US
dc.subject.otherFpgaen_US
dc.subject.otherMachine Learningen_US
dc.subject.otherRemote Sensingen_US
dc.subject.otherRemote Sensingen_US
dc.subject.otherSatellitesen_US
dc.subject.otherTarget Detectionen_US
dc.subject.otherTrainingen_US
dc.titleFPGA-based implementation of a CNN architecture for the on-board processing of very high resolution remote sensing imagesen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typearticleen_US
dc.identifier.doi10.1109/JSTARS.2022.3169330en_US
dc.identifier.scopus85128628681-
dc.contributor.orcidNO DATA-
dc.contributor.orcidNO DATA-
dc.contributor.orcidNO DATA-
dc.contributor.orcidNO DATA-
dc.contributor.orcidNO DATA-
dc.contributor.authorscopusid55812965200-
dc.contributor.authorscopusid57606471000-
dc.contributor.authorscopusid56333613300-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid35609452100-
dc.identifier.eissn2151-1535-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.date.coverdateEnero 2022en_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr1,264
dc.description.jcr5,5
dc.description.sjrqQ1
dc.description.jcrqQ1
dc.description.scieSCIE
dc.description.miaricds10,6
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-5033-9809-
crisitem.author.orcid0000-0001-7590-7895-
crisitem.author.orcid0000-0002-4303-3051-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameNeris Tomé, Romén-
crisitem.author.fullNameRodriguez Molina, Adrian-
crisitem.author.fullNameGuerra Hernández,Raúl Celestino-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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