Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/111099
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Pérez Suárez, Santiago Tomás | en_US |
dc.contributor.author | Robaina, Carlos Osorio | en_US |
dc.contributor.author | Vásquez Núñez, José L. | en_US |
dc.contributor.author | Alonso Hernández, Jesús Bernardino | en_US |
dc.contributor.author | Travieso González, Carlos Manuel | en_US |
dc.date.accessioned | 2021-07-26T12:03:49Z | - |
dc.date.available | 2021-07-26T12:03:49Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.isbn | 978-960-474-359-9 | en_US |
dc.identifier.issn | 1790-5117 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/111099 | - |
dc.description.abstract | In this work a methodology of a parallelized neural network has been designed. It explains a way to design a Neural Network using Mathworks and Xilinx Tools. Initially, the floating point algorithm was evaluated using MatlabNeural Network Toolbox. Afterwards, the fixed point algorithm was designed on a Field Programmable Gate Array (FPGA).The architecture was fully parallelized. The design tool used is System Generator of Xilinx, which works over Simulink. Finally the System Generator design is compiled for Xilinx Integrated System Environment (ISE). | en_US |
dc.language | eng | en_US |
dc.publisher | WSEAS Press | en_US |
dc.relation.ispartof | Recent advances in electrical engineering | en_US |
dc.source | Proceedings of the 8th WSEAS International Conference on Circuits, Systems, Signal and Telecommunications (CSST 2014) | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | Neural Network | en_US |
dc.subject.other | FPGA | en_US |
dc.subject.other | Floating point | en_US |
dc.subject.other | Fixed point | en_US |
dc.subject.other | Matlab | en_US |
dc.subject.other | Simulink | en_US |
dc.subject.other | System Generator | en_US |
dc.subject.other | ISE | en_US |
dc.title | Design Methodology of a Fully Parallelized Neural Network on a FPGA | en_US |
dc.type | info:eu-repo/semantics/conferenceobject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | 8th International Conference on Circuits, Systems, Signal and Telecommunications (CSST 2014) | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.utils.revision | No | en_US |
dc.identifier.ulpgc | Sí | en_US |
dc.contributor.buulpgc | BU-TEL | en_US |
item.grantfulltext | open | - |
item.fulltext | Con texto completo | - |
crisitem.author.dept | Departamento de Señales y Comunicaciones | - |
crisitem.author.dept | GIR IDeTIC: División de Procesado Digital de Señales | - |
crisitem.author.dept | IU para el Desarrollo Tecnológico y la Innovación | - |
crisitem.author.dept | Departamento de Señales y Comunicaciones | - |
crisitem.author.dept | GIR IDeTIC: División de Procesado Digital de Señales | - |
crisitem.author.dept | IU para el Desarrollo Tecnológico y la Innovación | - |
crisitem.author.dept | Departamento de Señales y Comunicaciones | - |
crisitem.author.orcid | 0000-0001-5702-4773 | - |
crisitem.author.orcid | 0000-0002-7866-585X | - |
crisitem.author.orcid | 0000-0002-4621-2768 | - |
crisitem.author.parentorg | IU para el Desarrollo Tecnológico y la Innovación | - |
crisitem.author.parentorg | IU para el Desarrollo Tecnológico y la Innovación | - |
crisitem.author.fullName | Pérez Suárez, Santiago Tomás | - |
crisitem.author.fullName | Alonso Hernández, Jesús Bernardino | - |
crisitem.author.fullName | Travieso González, Carlos Manuel | - |
crisitem.event.eventsstartdate | 10-01-2014 | - |
crisitem.event.eventsenddate | 12-01-2014 | - |
Colección: | Actas de congresos |
Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.