Hardware/Software partitioning based on Simulated Annealing

Abstract

A software implementation often can not satisfy embedded systems timing constraints. This problem can be solved by adding specifíc hardware to the system. Lately, it has been developed some design methodologies for this type of hardware/software systems. Our research group is developing a hardware/ software codesign environment for designing this type of systems. In this paper, we present our Hw/Sw partitioning algorithm that is based on simulated annealing. Main contribution is the foUowing: it supports process-level pipelining and estimates system power consumption. Thus, system designer can explore the design space to make latency, área and power trade-offs.