Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/107312
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dc.contributor.authorSantos Falcón, Lucanaen_US
dc.contributor.authorGómez Rebordinos, Anaen_US
dc.contributor.authorSarmiento Rodríguez, Robertoen_US
dc.date.accessioned2021-05-27T08:09:11Z-
dc.date.available2021-05-27T08:09:11Z-
dc.date.issued2020en_US
dc.identifier.issn0018-9251en_US
dc.identifier.urihttp://hdl.handle.net/10553/107312-
dc.description.abstractThis paper presents the modeling, design, and implementation of two intellectual property (IP) cores that are compliant with the consultative committee for space data systems (CCSDS) 121.0-B-2 and CCSDS 123.0-B-1 lossless satellite image compression standards. The CCSDS 121.0-B-2 describes a lossless universal compressor based on a Rice adaptive encoding. The CCSDS 123.0-B-1 standard describes a lossless algorithm specifically designed for efficient on-board compression of hyperspectral and multispectral images, and it is based on a prediction and entropy-based encoding structure. Two options are offered for the latter: the sample-adaptive and the block-adaptive encoder, which corresponds to the CCSDS 121.0-B-2 algorithm. These IP cores have been designed as independent compressors, but they can be easily combined in a plug-and-play fashion to be used together thanks to a dedicated interface. Additionally, standard interfaces are provided for configuration and external memory access. The design process encompasses the consideration of several different hardware architectures in order to maximize throughput and optimize the requirements of on-board resources at the same time. Both IPs are compliant with the high degree of configurability considered in the standard. The obtained VHDL code is completely technology independent, so it can be used to target any field-programmable gate array (FPGA) or ASIC of interest in the space environment, aiming to perform efficiently compression in satellites despite the inherent constraints of these devices. Results are reported as implementation results for the FPGA devices that are currently considered most representative and suited for on-board use from Xilinx and Microsemi families. In particular, the CCSDS123 IP core reaches for the Virtex5 FX130 a throughput of 153.5 Msamples per second, comprising only 5% of the look-up table (LUTs) in the device.en_US
dc.languageengen_US
dc.relation.ispartofIEEE Transactions on Aerospace and Electronic Systemsen_US
dc.sourceIEEE Transactions on Aerospace and Electronic Systems [ISSN 0018-9251], v. 56(2), p. 1120-1138, (Abril 2020)en_US
dc.subject3325 Tecnología de las telecomunicacionesen_US
dc.subject.otherImage codingen_US
dc.subject.otherHyperspectral imagingen_US
dc.subject.otherSatellitesen_US
dc.subject.otherField programmable gate arraysen_US
dc.subject.otherStandardsen_US
dc.titleImplementation of CCSDS Standards for Lossless Multispectral and Hyperspectral Satellite Image Compressionen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typearticleen_US
dc.identifier.doi10.1109/TAES.2019.2929971en_US
dc.identifier.issue2-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr1,137
dc.description.jcr4,102
dc.description.sjrqQ1
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSantos Falcón, Lucana-
crisitem.author.fullNameGómez Rebordinos, Ana-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
Colección:Artículos
miniatura
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