High performance bootstrapped CMOS dual supply level shifter for 0.5V input and 1V output

Abstract

This paper presents the design of a highly area efficient bootstrapped CMOS level shifter (vj-level shifter). The proposed vj-level shifter uses a single bootstrap capacitor to minimise active area and to maintain the voltage difference between the gates of output pull-up PMOS and output pull down NMOS transistors. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (2pF), vj-level shifter has a lower active area (93%), and energy delay product (15%) than the reference level shifter circuit (ts-level shifter). Also vj-level shifter has very small effective input capacitance in comparison with ts level shifter because the first does not need extra bootstrap capacitor connected with the input.