Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/76421
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dc.contributor.authorCaba, Juliánen_US
dc.contributor.authorDíaz, Maríaen_US
dc.contributor.authorBarba, Jesúsen_US
dc.contributor.authorGuerra Yanez, Raúlen_US
dc.contributor.authorde la Torre, Jose A.en_US
dc.contributor.authorLópez, Sebastiánen_US
dc.date.accessioned2020-12-09T09:23:44Z-
dc.date.available2020-12-09T09:23:44Z-
dc.date.issued2020en_US
dc.identifier.issn2072-4292en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/76421-
dc.description.abstractRemote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.en_US
dc.languageengen_US
dc.relation.ispartofRemote Sensingen_US
dc.sourceRemote Sensing [EISSN 2072-4292], v. 12 (22), 3741, p. 1-37, (Noviembre 2020)en_US
dc.subject220990 Tratamiento digital. Imágenesen_US
dc.subject.otherFPGAen_US
dc.subject.otherGPUen_US
dc.subject.otherHyperspectral Imagingen_US
dc.subject.otherLossy Compressionen_US
dc.subject.otherOn-Board Processingen_US
dc.subject.otherParallel Computingen_US
dc.subject.otherReal-Time Performanceen_US
dc.subject.otherUAVen_US
dc.titleFpga-based on-board hyperspectral imaging compression: Benchmarking performance and energy efficiency against gpu implementationsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.3390/rs12223741en_US
dc.identifier.scopus85096214622-
dc.contributor.authorscopusid55961635100-
dc.contributor.authorscopusid57192832495-
dc.contributor.authorscopusid13006950500-
dc.contributor.authorscopusid56333613300-
dc.contributor.authorscopusid57212149514-
dc.contributor.authorscopusid57187722000-
dc.identifier.eissn2072-4292-
dc.description.lastpage37en_US
dc.identifier.issue22-
dc.description.firstpage1en_US
dc.relation.volume12en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.description.notasThis article belongs to the Special Issue Remote Sensing Data Compressionen_US
dc.utils.revisionen_US
dc.date.coverdateNoviembre 2020en_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr1,285
dc.description.jcr4,848
dc.description.sjrqQ1
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-2670-8149-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameDíaz Martín,María-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
Colección:Artículos
miniatura
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