Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/74657
DC FieldValueLanguage
dc.contributor.authorCazorla, Francisco J.en_US
dc.contributor.authorFernández, Enriqueen_US
dc.contributor.authorKnijnenburg, Peter M.W.en_US
dc.contributor.authorRamirez, Alexen_US
dc.contributor.authorSakellariou, Rizosen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2020-10-05T19:46:08Z-
dc.date.available2020-10-05T19:46:08Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1058-3en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/74657-
dc.description.abstractMost research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a workload. In this paper, we discuss a new problem not previously addressed in the SMT literature. We call this problem Workload Execution Time (WET) minimization. It consists of reducing the total execution time of all threads in a workload. This problem arises in parallel applications, where it is common for a single master thread to spawn several child jobs. The master job cannot continue until all child jobs have finished. Reducing the overall execution time is important to speedup the application. This paper is a first step in analyzing this problem. First, we analyze the WET provided by the best fetch policies aimed at improving throughput/fairness. We demonstrate that these policies achieve less than optimum performance. We show that, on average, for the workloads evaluated in this paper, there is space for improvement of up to 18 percentage points. It follows that novel mechanisms trying to reduce WET are required to speedup parallel applications.en_US
dc.languageengen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.sourceProceedings - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007, p. 66-73, (Diciembre 2007)en_US
dc.subject1203 Ciencia de los ordenadoresen_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.titleOn the problem of minimizing workload execution time in SMT processorsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007en_US
dc.identifier.doi10.1109/ICSAMOS.2007.4285735en_US
dc.identifier.scopus47749155678-
dc.contributor.authorscopusid55129883300-
dc.contributor.authorscopusid36476145100-
dc.contributor.authorscopusid6603587864-
dc.contributor.authorscopusid7401734996-
dc.contributor.authorscopusid6701361478-
dc.contributor.authorscopusid24475914200-
dc.description.lastpage73en_US
dc.description.firstpage66en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.date.coverdateDiciembre 2007en_US
dc.identifier.conferenceidevents121347-
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.fullNameFernández García, Enrique-
crisitem.event.eventsstartdate16-07-2007-
crisitem.event.eventsenddate19-07-2007-
Appears in Collections:Actas de congresos
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