Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/73913
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Das, Rina | en_US |
dc.contributor.author | Fay, D. Q. M. | en_US |
dc.contributor.author | Das, Pradip K. | en_US |
dc.date.accessioned | 2020-08-02T16:19:59Z | - |
dc.date.available | 2020-08-02T16:19:59Z | - |
dc.date.issued | 1992 | en_US |
dc.identifier.issn | 0165-6074 | en_US |
dc.identifier.other | WoS | - |
dc.identifier.uri | http://hdl.handle.net/10553/73913 | - |
dc.description.abstract | The present work describes two methods for allocating m precedence-constrained tasks to n identical processors for optimal execution, uniform static load balancing and minimum interprocessor communication. The comparative studies made between two methods, the Simulated Annealing and a well-chosen Heuristic, indicate the suitability of the latter for complex precedence graphs. Examples from Matrix algebra have been chosen for the experiments. The resulting methods can be readily applied to optimize performance of practical problems on distributed memory parallel processor systems such as transputer-based systems. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Microprocessing and Microprogramming | en_US |
dc.source | Microprocessing and Microprogramming [ISSN 0165-6074], v. 35 (1-5), p. 237-244, (Septiembre 1992) | en_US |
dc.subject | 3325 Tecnología de las telecomunicaciones | en_US |
dc.title | Allocation of precedence-constrained tasks to parallel processors for optimal execution | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | Conference proceedings | en_US |
dc.relation.conference | 18 th Euromicro Symposium on Microprocessing and Microprogramming | en_US |
dc.identifier.doi | 10.1016/0165-6074(92)90322-X | en_US |
dc.identifier.scopus | 0026917377 | - |
dc.identifier.isi | A1992JN55700041 | - |
dc.contributor.authorscopusid | 55031238900 | - |
dc.contributor.authorscopusid | 24457147900 | - |
dc.contributor.authorscopusid | 16233201700 | - |
dc.description.lastpage | 244 | en_US |
dc.identifier.issue | 1-5 | - |
dc.description.firstpage | 237 | en_US |
dc.relation.volume | 35 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.contributor.daisngid | 26311450 | - |
dc.contributor.daisngid | 2523274 | - |
dc.contributor.daisngid | 1158563 | - |
dc.description.notas | Session C2: Parallel systems development tools | en_US |
dc.description.numberofpages | 8 | en_US |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | WOS:DAS, R | - |
dc.contributor.wosstandard | WOS:FAY, DQM | - |
dc.contributor.wosstandard | WOS:DAS, PK | - |
dc.date.coverdate | Enero 1992 | en_US |
dc.identifier.ulpgc | Sí | es |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.event.eventsstartdate | 14-09-1992 | - |
crisitem.event.eventsenddate | 17-09-1992 | - |
Colección: | Actas de congresos |
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