Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/72825
Título: Adding a vector unit to a superscalar processor
Autores/as: Quintana, Francisca 
Corbal, Jesús
Espasa, Roger
Valero, Mateo
Clasificación UNESCO: 330406 Arquitectura de ordenadores
Fecha de publicación: 1999
Conferencia: Proceedings of the 1999 13th ACM International Conference on Supercomputing, ICS'99 
Resumen: The focus of this paper is on adding a vector unit to a superscalar core, as a way to scale current state of the art superscalar processors. The proposed architecture has a vector register file that shares functional units both with the integer datapath and with the floating point datapath. A key point in our proposal is the design of a high performance cache interface that delivers high bandwidth to the vector unit at a low cost and low latency. We propose a double-banked cache with alignment circuitry to serve vector accesses and we study two cache hierarchies: one feeds the vector unit from the L1; the other from the L2. Our results show that large IPU values (higher than 10 in some cases) can be achieved. Moreover the scalability of our architecture simply requires addition of functional units, without requiring more issue bandwidth. As a consequence, the proposed vector unit achieves high performance for numerical and multimedia codes with minimal impact on the cycle time of the processor or on the performance of integer codes.
URI: http://hdl.handle.net/10553/72825
ISBN: 1-58113-164-X
DOI: 10.1145/305138.305148
Fuente: ICS '99: Proceedings of the 13th international conference on Supercomputing, p. 1-10, (1999)
Colección:Actas de congresos
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