Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/72822
Campo DC Valoridioma
dc.contributor.authorQuintana, Franciscaen_US
dc.contributor.authorEspasa, Rogeren_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2020-05-29T12:59:56Z-
dc.date.available2020-05-29T12:59:56Z-
dc.date.issued1999en_US
dc.identifier.isbn978-3-540-48516-2en_US
dc.identifier.issn0302-9743en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/72822-
dc.description.abstractThis paper presents a comparison between superscalar and vector processors. First, we start with a detailed ISA analysis of the vector machine, including data related to masked execution, vector length and vector first facilities. Then we present a comparison of the two models at the instruction set architecture (ISA) level that shows that the vector model has several advantages: executes fewer instructions, fewer overall operations, and generally executes fewer memory accesses. We then analyse both models in terms of speculative execution, each one in its context. Results show that superscalar processors make an extensive use of speculation and that there is a large amount of misspeculated instructions. In the vector model, speculation is achieved using vector masks and, in general, fewer operations are misspeculated.en_US
dc.languageengen_US
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.sourceHernández V., Palma J.M.L.M., Dongarra J.J. (eds) Vector and Parallel Processing – VECPAR’98. Lecture Notes in Computer Science, [ISSN 0302-9743], v. 1573, p. 548-560. Springer, Berlin, Heidelberg. (1999)en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.titleAn ISA comparison between superscalar and vector processorsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference3rd International Conference on Vector And Parallel Processing (VECPAR 98)en_US
dc.identifier.doi10.1007/10703040_41en_US
dc.identifier.scopus84957887397-
dc.identifier.isi000084209000041-
dc.contributor.authorscopusid7004920817-
dc.contributor.authorscopusid56619611500-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1611-3349-
dc.description.lastpage560en_US
dc.description.firstpage548en_US
dc.relation.volume1573en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid30500693-
dc.contributor.daisngid1455259-
dc.contributor.daisngid41870-
dc.description.numberofpages13en_US
dc.identifier.eisbn978-3-540-66228-0-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Quintana, F-
dc.contributor.wosstandardWOS:Espasa, R-
dc.contributor.wosstandardWOS:Valero, M-
dc.date.coverdateEnero 1999en_US
dc.identifier.conferenceidevents120267-
dc.identifier.conferenceidevents121570-
dc.identifier.ulpgces
dc.description.jcr0,872
dc.description.jcrqQ1
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate21-06-1998-
crisitem.event.eventsenddate23-06-1998-
crisitem.author.deptGIR IUCES: Computación inteligente, percepción y big data-
crisitem.author.deptIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-8951-5040-
crisitem.author.parentorgIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.fullNameQuintana Domínguez, Francisca Candelaria-
Colección:Actas de congresos
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