Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/72777
Campo DC Valoridioma
dc.contributor.authorQuintana, Franciscaen_US
dc.contributor.authorCorbal, Jesúsen_US
dc.contributor.authorEspasa, Rogeren_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2020-05-26T13:55:36Z-
dc.date.available2020-05-26T13:55:36Z-
dc.date.issued2003en_US
dc.identifier.issn1432-4350en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/72777-
dc.description.abstractThis paper analyzes the performance of vector-dominated regions of code in numerical and multimedia applications in a superscalar + vector architecture and compares it with an eight-way superscalar processor. The ability to split a program's execution into scalar and vector regions allows us to show that (1) as expected, the vector unit is much better than the wide-issue superscalar at executing the vector-dominated regions of the code; (2) on the scalar regions, the eight-way superscalar, although better than a four-way superscalar, is clearly not worth the extra complexity in terms of extra transistors and potential cycle-time limitations. Overall, the vector-enhanced superscalar is from 6% to 303% better than an eight-way superscalar. We also present detailed data on the performance of the memory system, which is usually the key limiting factor when running numerical and multimedia applications. We evaluate two additional cache designs that try to alleviate problems created by non-unit stride memory references.en_US
dc.languageengen_US
dc.relation0995en_US
dc.relation.ispartofTheory of Computing Systemsen_US
dc.sourceTheory of Computing Systems [ISSN 1432-4350] ,v. 36 (5), p. 575-593, (Septiembre-Octubre 2003)en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject.otherMultimedia applicationen_US
dc.subject.otherCache lineen_US
dc.subject.otherVectorizable numericalen_US
dc.subject.otherCache hierarchyen_US
dc.subject.otherMultimedia programen_US
dc.titleA cost-effective architecture for vectorizable numerical and multimedia applicationsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s00224-003-1088-4en_US
dc.identifier.scopus0142259782-
dc.identifier.isi000185228200009-
dc.contributor.authorscopusid7004920817-
dc.contributor.authorscopusid6603181643-
dc.contributor.authorscopusid56619611500-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1433-0490-
dc.description.lastpage593en_US
dc.identifier.issue5-
dc.description.firstpage575en_US
dc.relation.volume36en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid6058715-
dc.contributor.daisngid3776216-
dc.contributor.daisngid12960531-
dc.contributor.daisngid41870-
dc.description.numberofpages19en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Quintana, F-
dc.contributor.wosstandardWOS:Corbal, J-
dc.contributor.wosstandardWOS:Espasa, R-
dc.contributor.wosstandardWOS:Valero, M-
dc.date.coverdateSeptiembre 2003en_US
dc.identifier.ulpgcen_US
dc.description.jcr0,364
dc.description.jcrqQ3
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUCES: Computación inteligente, percepción y big data-
crisitem.author.deptIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-8951-5040-
crisitem.author.parentorgIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.fullNameQuintana Domínguez, Francisca Candelaria-
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