Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/52612
DC FieldValueLanguage
dc.contributor.authorSantos, Lucanaen_US
dc.contributor.authorBerrojo, Luisen_US
dc.contributor.authorMoreno, Javieren_US
dc.contributor.authorLópez Feliciano, José Franciscoen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.date.accessioned2018-12-05T08:58:54Z-
dc.date.available2018-12-05T08:58:54Z-
dc.date.issued2016en_US
dc.identifier.issn1939-1404en_US
dc.identifier.urihttp://hdl.handle.net/10553/52612-
dc.description.abstractAn efficient compression of hyperspectral images on-board satellites is mandatory in current and future space missions in order to save bandwidth and storage space. Reducing the data volume in space is a challenge that has been faced with a twofold approach: To propose new highly efficient compression algorithms; and to present technologies and strategies to execute the compression in the hardware available on-board. The Consultative Committee for Space Data Systems (CCSDS), a consortium of the major space agencies in the world, has recently issued the CCSDS 123 standard for multispectral and hyperspectral image (MHI) compression, with the aim of facilitating the inclusion of on-board compression on satellites by the space industry. In this paper, we present a low-complexity feld programmable gate arrays (FPGAs) implementation of this recent CCSDS 123 standard, which demonstrates its main features in terms of compression efficiency and suitability for an implementation on the available on-board technologies. A hardware architecture is conceived and designed with the aim of achieving low hardware occupancy and high performance on a space-qualified FPGA from the Microsemi RTAX family. The resulting FPGA implementation is therefore suitable for on-board compression. The effect of the several CCSDS-123 configuration parameters on the compression efficiency and hardware complexity is taken into consideration to provide flexibility in such a way that the implementation can be adapted to different application scenarios. Synthesis results show a very low occupancy of 34% and a maximum frequency of 43 MHz on a space-qualified RTAX1000S. The benefits of the proposed implementation are further evidenced by a demonstrator, which is implemented on a commercial prototyping board from Xilinx. Finally, a comparison with other FPGA implementations of on-board data compression algorithms is provided.en_US
dc.languageengen_US
dc.relation.ispartofIEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensingen_US
dc.sourceIEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing [ISSN 1939-1404], v. 9 (7364166), p. 757-770en_US
dc.subject220921 Espectroscopiaen_US
dc.subject.otherFeld programmable gate array (FPGA)en_US
dc.subject.otherHyperspectral imagesen_US
dc.subject.otherOn-board compressionen_US
dc.titleMultispectral and hyperspectral lossless compressor for space applications (HyLoC): A low-complexity FPGA implementation of the CCSDS 123 standarden_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSTARS.2015.2497163en_US
dc.identifier.scopus84962237683-
dc.identifier.isi000370877600017-
dc.contributor.authorscopusid54391653200-
dc.contributor.authorscopusid6505938449-
dc.contributor.authorscopusid57206885689-
dc.contributor.authorscopusid7401925356-
dc.contributor.authorscopusid7404444793-
dc.contributor.authorscopusid35609452100-
dc.description.lastpage770en_US
dc.identifier.issue2-
dc.description.firstpage757en_US
dc.relation.volume9en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid29585558-
dc.contributor.daisngid4645895-
dc.contributor.daisngid1598612-
dc.contributor.daisngid2138004-
dc.contributor.daisngid116294-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Santos, L-
dc.contributor.wosstandardWOS:Berrojo, L-
dc.contributor.wosstandardWOS:Moreno, J-
dc.contributor.wosstandardWOS:Lopez, JF-
dc.contributor.wosstandardWOS:Sarmiento, R-
dc.date.coverdateFebrero 2016en_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr1,427
dc.description.jcr2,913
dc.description.sjrqQ1
dc.description.jcrqQ1
dc.description.scieSCIE
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-6304-2801-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSantos Falcón, Lucana-
crisitem.author.fullNameLópez Feliciano, José Francisco-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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