Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/52495
Campo DC Valoridioma
dc.contributor.authorCervero, T.en_US
dc.contributor.authorOtero, A.en_US
dc.contributor.authorLópez, S.en_US
dc.contributor.authorde la Torre, E.en_US
dc.contributor.authorCallicó, G. M.en_US
dc.contributor.authorRiesgo, T.en_US
dc.contributor.authorSarmiento, R.en_US
dc.date.accessioned2018-11-27T14:09:59Z-
dc.date.available2018-11-27T14:09:59Z-
dc.date.issued2016en_US
dc.identifier.issn1861-8200en_US
dc.identifier.urihttp://hdl.handle.net/10553/52495-
dc.description.abstractThe deblocking filter (DF) is one of the most complex functional cores of the H.264/AVC and SVC codecs. Its computational cost is heavily dependent on the video profile and the selected scalability level. With the goal of providing faster and better solutions, developers are focused on designing hardware architectures. Thus, it is possible taking advantage of multitasking, reusability and parallelization techniques. In this context, this work proposes a scalable DF architecture that is able to adapt its structure and performance to different video configurations, due to its modular and regular structure. The scalability feature avoids redesigning the whole architecture in case of the environmental demands or the configuration settings change. These facts mean savings in terms of design productivity and silicon area by adapting the necessary logical resources to each condition. Furthermore, regarding the data dependences involved in the H.264/AVC DF algorithm, the proposed architecture relies on an improved version of a traditional wavefront parallelization strategy, also proposed by the authors. This solution reduces the amount of clock cycles needed to filter a video frame as compared to traditional strategies. Implementation results, in an FPGA Virtex-5, demonstrate the performance benefits of this flexible solution as compared to some rigid state-of-the-art deblocking filter approaches.en_US
dc.languageengen_US
dc.relation.ispartofJournal of Real-Time Image Processingen_US
dc.sourceJournal of Real-Time Image Processing[ISSN 1861-8200],v. 12, p. 81-105en_US
dc.subject220990 Tratamiento digital. Imágenesen_US
dc.subject.otherDeblocking filteren_US
dc.subject.otherFPGAen_US
dc.subject.otherH.264/AVCen_US
dc.subject.otherMacroblocken_US
dc.subject.otherScalabilityen_US
dc.titleA scalable H.264/AVC deblocking filter architectureen_US
dc.typeinfo:eu-repo/semantics/Articlees
dc.typeArticlees
dc.relation.conferenceSPIE Conference on Real-Time Image and Video Processing as part of SPIE Photonics Europe Conference
dc.identifier.doi10.1007/s11554-013-0359-9
dc.identifier.scopus84879363975
dc.identifier.isi000376651600008
dc.contributor.authorscopusid34978225000
dc.contributor.authorscopusid35868116400
dc.contributor.authorscopusid57187722000
dc.contributor.authorscopusid6603668216
dc.contributor.authorscopusid56006321500
dc.contributor.authorscopusid6602760583
dc.contributor.authorscopusid35609452100
dc.description.lastpage105-
dc.identifier.issue1-
dc.description.firstpage81-
dc.relation.volume12-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid5352902
dc.contributor.daisngid34716851
dc.contributor.daisngid465777
dc.contributor.daisngid626981
dc.contributor.daisngid506422
dc.contributor.daisngid273151
dc.contributor.daisngid116294
dc.contributor.wosstandardWOS:Cervero, T
dc.contributor.wosstandardWOS:Otero, A
dc.contributor.wosstandardWOS:Lopez, S
dc.contributor.wosstandardWOS:de la Torre, E
dc.contributor.wosstandardWOS:Callico, GM
dc.contributor.wosstandardWOS:Riesgo, T
dc.contributor.wosstandardWOS:Sarmiento, R
dc.date.coverdateJunio 2016
dc.identifier.ulpgces
dc.description.sjr0,313
dc.description.jcr2,01
dc.description.sjrqQ3
dc.description.jcrqQ2
dc.description.scieSCIE
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameCervero García, Teresa Gloria-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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