|Title:||A scalable single-chip multi-processor architecture with on-chip RTOS kernel||Authors:||Theelen, B. D.
Verschueren, A. C.
Suárez, V. V.Reyes
Stevens, M. P.J.
|Keywords:||Networks||Issue Date:||2003||Publisher:||1383-7621||Journal:||Journal of Systems Architecture||Abstract:||Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a single-chip multi-processor for real-time (networked) embedded systems is the multi-microprocessor (MmuP). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper, we explore the main design issues of the architecture platform on which the MmuP is based. In addition, synthesis results are presented for a lightweight configuration of this architecture platform. (C) 2003 Elsevier B.V. All rights reserved.||URI:||http://hdl.handle.net/10553/51888||ISSN:||1383-7621||DOI:||10.1016/S1383-7621(03)00101-2||Source:||Journal of Systems Architecture[ISSN 1383-7621],v. 49, p. 619-639|
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