Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50504
DC FieldValueLanguage
dc.contributor.authorFalcón, Ayoseen_US
dc.contributor.authorSantana, Oliverio J.en_US
dc.contributor.authorRamirez, Alexen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2018-11-24T16:33:07Z-
dc.date.available2018-11-24T16:33:07Z-
dc.date.issued2004en_US
dc.identifier.issn1740-0562en_US
dc.identifier.urihttp://hdl.handle.net/10553/50504-
dc.description.abstractExecuting multiple threads has proved to be an effective solution to partially hide latencies that appear in a processor. When a thread is stalled because of a long-latency operation is being processed, such as a memory access or a floating-point calculation, the processor can switch to another context so that another thread can take advantage of the idle resources. However, fetch stall conditions caused by a branch predictor delay are not hidden by current simultaneous multithreading (SMT) fetch designs, causing a performance drop due to the absence of instructions to execute. In this paper, we propose several solutions to reduce the effect of branch predictor delay in the performance of SMT processors. Firstly, we analyse the impact of varying the number of access ports. Secondly, we describe a decoupled implementation of an SMT fetch unit that helps to tolerate the predictor delay. Finally, we present an interthread pipelined branch predictor, based on creating a pipeline of interleaved predictions from different threads. Our results show that, combining all the proposed techniques, the performance obtained is similar to that obtained using an ideal, 1-cycle access branch predictor.en_US
dc.languageengen_US
dc.relation.ispartofInternational Journal of High Performance Computing and Networkingen_US
dc.sourceInternational Journal of High Performance Computing and Networking [ISSN 1740-0562], v. 2 (1), p. 11-21en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject.otherBranch predictor delayen_US
dc.subject.otherDecoupled predictoren_US
dc.subject.otherFetch engineen_US
dc.subject.otherPredictor pipeliningen_US
dc.subject.otherSMTen_US
dc.titleA latency-conscious SMT branch prediction architectureen_US
dc.typeinfo:eu-repo/semantics/articlees
dc.typeArticlees
dc.identifier.doi10.1504/IJHPCN.2004.009264en_US
dc.identifier.scopus84951714939-
dc.contributor.authorscopusid9733156400-
dc.contributor.authorscopusid7003605046-
dc.contributor.authorscopusid55837529000-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1740-0570-
dc.description.lastpage21-
dc.identifier.issue1-
dc.description.firstpage11-
dc.relation.volume2-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-7511-5783-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameSantana Jaria, Oliverio Jesús-
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