Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50503
DC FieldValueLanguage
dc.contributor.authorCristal, Adriánen_US
dc.contributor.authorSantana, Oliverio J.en_US
dc.contributor.authorValero, Mateoen_US
dc.contributor.authorMartínez, José F.en_US
dc.date.accessioned2018-11-24T16:32:39Z-
dc.date.available2018-11-24T16:32:39Z-
dc.date.issued2004en_US
dc.identifier.issn1544-3566en_US
dc.identifier.urihttp://hdl.handle.net/10553/50503-
dc.description.abstractThe continuously increasing gap between processor and memory speeds is a serious limitation to the performance achievable by future microprocessors. Currently, processors tolerate long-latency memory operations largely by maintaining a high number of in-flight instructions. In the future, this may require supporting many hundreds, or even thousands, of in-flight instructions. Unfortunately, the traditional approach of scaling up critical processor structures to provide such support is impractical at these levels, due to area, power, and cycle time constraints.In this paper we show that, in order to overcome this resource-scalability problem, the way in which critical processor resources are managed must be changed. Instead of simply upsizing the processor structures, we propose a smarter use of the available resources, supported by a selective checkpointing mechanism. This mechanism allows instructions to commit out of order, and makes a reorder buffer unnecessary. We present a set of techniques such as multilevel instruction queues, late allocation and early release of registers, and early release of load/store queue entries. All together, these techniques constitute what we call a kilo-instruction processor, an architecture that can support thousands of in-flight instructions, and thus may achieve high performance even in the presence of large memory access latencies.en_US
dc.languageengen_US
dc.relation.ispartofTransactions on Architecture and Code Optimizationen_US
dc.sourceACM Transactions on Architecture and Code Optimization [ISSN 1544-3566], v. 1 (4), p. 389-417en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject.otherDesignen_US
dc.subject.otherInstruction-level parallelismen_US
dc.subject.otherKilo-instruction processorsen_US
dc.subject.otherMemory wallen_US
dc.subject.otherMulticheckpointingen_US
dc.subject.otherPerformanceen_US
dc.titleToward kilo-instruction processorsen_US
dc.typeinfo:eu-repo/semantics/articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1145/1044823.1044825en_US
dc.identifier.scopus84988438049-
dc.contributor.authorscopusid55884958300-
dc.contributor.authorscopusid7003605046-
dc.contributor.authorscopusid24475914200-
dc.contributor.authorscopusid57194917906-
dc.identifier.eissn1544-3973-
dc.description.lastpage417en_US
dc.identifier.issue4-
dc.description.firstpage389en_US
dc.relation.volume1en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptSIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-7511-5783-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameSantana Jaria, Oliverio Jesús-
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