Micropipeline architecture for multiplier-less FIR filters

Título:	Micropipeline architecture for multiplier-less FIR filters
Autores/as:	Nooshabadi, S. Montiel-Nelson, J. A. Visweswaran, G. S. Nagchoudhurhi, D.
Clasificación UNESCO:	3307 Tecnología electrónica
Palabras clave:	Finite impulse response filter Clocks Very large scale integration CMOS technology Delay, et al.
Fecha de publicación:	1997
Publicación seriada:	Proceedings of the IEEE International Conference on VLSI Design
Resumen:	In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropipelined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.
URI:	https://accedacris.ulpgc.es/handle/10553/49698
ISBN:	0-8186-7755-4
Fuente:	Proceedings of the IEEE International Conference on VLSI Design, p. 451-456
Appears in Collections:	Actas de congresos

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