Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/49698
| Title: | Micropipeline architecture for multiplier-less FIR filters | Authors: | Nooshabadi, S. Montiel-Nelson, J. A. Visweswaran, G. S. Nagchoudhurhi, D. |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | Finite impulse response filter Clocks Very large scale integration CMOS technology Delay, et al |
Issue Date: | 1997 | Journal: | Proceedings of the IEEE International Conference on VLSI Design | Abstract: | In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropipelined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network. | URI: | http://hdl.handle.net/10553/49698 | ISBN: | 0-8186-7755-4 | Source: | Proceedings of the IEEE International Conference on VLSI Design, p. 451-456 |
| Appears in Collections: | Actas de congresos |
SCOPUSTM
Citations
5
checked on Nov 17, 2024
Page view(s)
31
checked on Feb 4, 2023
Google ScholarTM
Check
Altmetric
Share
Export metadata
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.