Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/48188
DC FieldValueLanguage
dc.contributor.authorOjeda-Guerra, C. N.en_US
dc.contributor.authorEsper-Chaín, R.en_US
dc.contributor.authorEstupiñán, M.en_US
dc.contributor.authorMacías, E.en_US
dc.contributor.authorSuárez, Á.en_US
dc.date.accessioned2018-11-23T19:38:06Z-
dc.date.available2018-11-23T19:38:06Z-
dc.date.issued1998en_US
dc.identifier.isbn3540649484en_US
dc.identifier.issn0302-9743en_US
dc.identifier.urihttp://hdl.handle.net/10553/48188-
dc.description.abstractThe parallelization of numerical algorithms is very important in scientific applications, but many points of this parallelization remain open today. Specifically, the overhead introduced by loading and unloading the data degrades the efficiency, and in a realistic approach should be taking into account for performance estimation. The authors of this paper present a way of overcoming the bottleneck of loading and unloading the data by overlapping computations and communications in a specific algorithm such as matrix-vector multiplication. Also, a way of mapping this algorithm in hardware is presented in order to demonstrate the parallelization methodology.en_US
dc.languageengen_US
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.sourceLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)[ISSN 0302-9743],v. 1482, p. 396-400en_US
dc.subject3325 Tecnología de las telecomunicacionesen_US
dc.subject.otheralgorithmen_US
dc.subject.otherparallelizationen_US
dc.subject.othermatrix-vector multiplicationen_US
dc.titleHardware mapping of a parallel algorithm for matrix-vector multiplication overlapping communications and computationsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference8th International Workshop on Field-Programmable Logic and Applications, FPL 1998en_US
dc.identifier.scopus1642273864-
dc.contributor.authorscopusid6506487977-
dc.contributor.authorscopusid6602504574-
dc.contributor.authorscopusid57092725000-
dc.contributor.authorscopusid7005482663-
dc.contributor.authorscopusid7202765632-
dc.description.lastpage400en_US
dc.description.firstpage396en_US
dc.relation.volume1482en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.date.coverdateEnero 1998en_US
dc.identifier.conferenceidevents121274-
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptIngeniería Telemática-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptIngeniería Electrónica y Automática-
crisitem.author.deptIUCTC: Arquitectura y Concurrencia-
crisitem.author.deptIU de Ciencias y Tecnologías Cibernéticas-
crisitem.author.deptIngeniería Telemática-
crisitem.author.deptIUCTC: Arquitectura y Concurrencia-
crisitem.author.deptIU de Ciencias y Tecnologías Cibernéticas-
crisitem.author.deptIngeniería Telemática-
crisitem.author.orcid0000-0002-8381-969X-
crisitem.author.orcid0000-0002-9085-8398-
crisitem.author.orcid0000-0002-3043-7161-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Ciencias y Tecnologías Cibernéticas-
crisitem.author.parentorgIU de Ciencias y Tecnologías Cibernéticas-
crisitem.author.fullNameOjeda Guerra, Carmen Nieves-
crisitem.author.fullNameEsper-Chaín Falcón, Roberto-
crisitem.author.fullNameMacías López, Elsa María-
crisitem.author.fullNameSuárez Sarmiento, Álvaro-
crisitem.event.eventsstartdate31-08-1998-
crisitem.event.eventsenddate03-09-1998-
Appears in Collections:Actas de congresos
Show simple item record

SCOPUSTM   
Citations

1
checked on Jul 25, 2021

Page view(s)

17
checked on Jul 17, 2021

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.