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Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/47685
Campo DC Valoridioma
dc.contributor.authorDias, T.en_US
dc.contributor.authorLopez, S.en_US
dc.contributor.authorRoma, N.en_US
dc.contributor.authorSousa, L.en_US
dc.contributor.otherRoma, Nuno-
dc.contributor.otherLopez, Sebastian-
dc.contributor.otherDias, Tiago-
dc.contributor.otherSousa, Leonel-
dc.date.accessioned2018-11-23T15:34:28Z-
dc.date.available2018-11-23T15:34:28Z-
dc.date.issued2011en_US
dc.identifier.issn0098-3063en_US
dc.identifier.urihttp://hdl.handle.net/10553/47685-
dc.description.abstractA new high throughput and scalable architecture for unified transform coding in H.264/AVC is proposed in this paper. Such flexible structure is capable of computing all the 4x4 and 2x2 transforms for Ultra High Definition Video (UHDV) applications (4320x7680@ 30fps) in real-time and with low hardware cost. These significantly high performance levels were proven with the implementation of several different configurations of the proposed structure using both FPGA and ASIC 90 nm technologies. In addition, such experimental evaluation also demonstrated the high area efficiency of the proposed architecture, which in terms of Data Throughput per Unit of Area (DTUA) is at least 1.5 times more efficient than its more prominent related designs(1).en_US
dc.languageengen_US
dc.publisher0098-3063-
dc.relation.ispartofIEEE Transactions on Consumer Electronicsen_US
dc.sourceIeee Transactions On Consumer Electronics[ISSN 0098-3063],v. 57 (2), p. 936-944en_US
dc.subject220990 Tratamiento digital. Imágenesen_US
dc.subject.otherTransform codingen_US
dc.subject.otherArraysen_US
dc.subject.otherKernelen_US
dc.subject.otherStreaming mediaen_US
dc.subject.otherVideo codingen_US
dc.titleA flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCE.2011.5955243en_US
dc.identifier.scopus79960929422-
dc.identifier.isi000293728700086-
dcterms.isPartOfIeee Transactions On Consumer Electronics-
dcterms.sourceIeee Transactions On Consumer Electronics[ISSN 0098-3063],v. 57 (2), p. 936-944-
dc.contributor.authorscopusid35093983900-
dc.contributor.authorscopusid11540058800-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid6602399540-
dc.contributor.authorscopusid7004775548-
dc.description.lastpage944en_US
dc.identifier.issue5955243-
dc.description.firstpage936en_US
dc.relation.volume57en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:000293728700086-
dc.contributor.daisngid3450196-
dc.contributor.daisngid465777-
dc.contributor.daisngid454304-
dc.contributor.daisngid74430-
dc.identifier.investigatorRIDC-5586-2008-
dc.identifier.investigatorRIDL-8108-2014-
dc.identifier.investigatorRIDH-4265-2011-
dc.identifier.investigatorRIDB-2749-2009-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Dias, T-
dc.contributor.wosstandardWOS:Lopez, S-
dc.contributor.wosstandardWOS:Roma, N-
dc.contributor.wosstandardWOS:Sousa, L-
dc.date.coverdateMayo 2011en_US
dc.identifier.ulpgcSíes
dc.description.sjr0,512
dc.description.jcr0,941
dc.description.sjrqQ1
dc.description.jcrqQ2
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
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