Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/46916
DC FieldValueLanguage
dc.contributor.authorGonzález, B.en_US
dc.contributor.authorIñiguez, B.en_US
dc.contributor.authorLázaro, A.en_US
dc.contributor.authorCerdeira, A.en_US
dc.contributor.otherLazaro, Antonio-
dc.contributor.otherGonzalez, Benito-
dc.date.accessioned2018-11-23T09:23:22Z-
dc.date.available2018-11-23T09:23:22Z-
dc.date.issued2011en_US
dc.identifier.issn0268-1242en_US
dc.identifier.urihttp://hdl.handle.net/10553/46916-
dc.description.abstractSelf-heating in planar double-gate (DG) MOSFETs is numerically studied under static operating conditions. In order to correctly predict the lattice temperature inside the device and, consequently, the drain current, factors such as the reduction in thermal conductivity of thin films (temperature dependent), the influence of the buried oxide layer, the necessity of a hydrodynamic model and quantization are analysed to evidence their impact on a proper simulation of the dc transistor performance. This paper also shows that DG MOSFETs can be thermally optimized using flare extensions in all terminals and mid-gap gate metals with high thermal conductivity. Moreover, the influence of gate length and channel thickness on the peak temperature rise is studied. Other major technological changes, such as eliminating thin oxide films from channel extensions and using AlN instead of SiO2, are also discussed.en_US
dc.languageengen_US
dc.publisher0268-1242-
dc.relation.ispartofSemiconductor Science and Technologyen_US
dc.sourceSemiconductor Science and Technology[ISSN 0268-1242],v. 26 (095014)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherThermal-Conductivity
dc.subject.otherSoi Mosfets
dc.subject.otherTransport
dc.subject.otherSimulation
dc.subject.otherPrediction
dc.subject.otherInversion
dc.subject.otherDevice
dc.subject.otherLayers
dc.subject.otherModel
dc.titleNumerical dc self-heating in planar double-gate MOSFETsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1088/0268-1242/26/9/095014
dc.identifier.scopus80052013979-
dc.identifier.isi000293904400016-
dcterms.isPartOfSemiconductor Science And Technology-
dcterms.sourceSemiconductor Science And Technology[ISSN 0268-1242],v. 26 (9)-
dc.contributor.authorscopusid56082155300-
dc.contributor.authorscopusid55148428400-
dc.contributor.authorscopusid56036357200-
dc.contributor.authorscopusid7003780995-
dc.identifier.issue095014-
dc.relation.volume26en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:000293904400016-
dc.contributor.daisngid1092737-
dc.contributor.daisngid91160-
dc.contributor.daisngid56325-
dc.contributor.daisngid137230-
dc.identifier.investigatorRIDJ-6076-2014-
dc.identifier.investigatorRIDH-6803-2015-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Gonzalez, B
dc.contributor.wosstandardWOS:Iniguez, B
dc.contributor.wosstandardWOS:Lazaro, A
dc.contributor.wosstandardWOS:Cerdeira, A
dc.date.coverdateSeptiembre 2011
dc.identifier.ulpgces
dc.description.sjr1,01
dc.description.jcr1,723
dc.description.sjrqQ2
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0001-6864-9736-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGonzález Pérez, Benito-
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