A compact layout technique for reducing switching current effects in high speed circuits

Abstract

A full-custom layout style and its cell model are presented. Its power supply and ground rails distribution is not only of very low self-inductance, but it is also independent of cell dimensions. Cell layouts following the proposed model reduce greatly switching current effects at high frequency. The underlying cell architecture is regular and suitable to design automation without sacrificing any advantages of the full-custom design. Layout channel density of a subset of MCNC'91 two-level circuit benchmarks have been obtained. Comparisons demonstrate that the layout of combinational circuits in the high speed cell model are compact and minimize the routing area. A cell compiler has been used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. It is shown that the cell and macrocell compiler generates complex and compact layouts. The technique is demonstrated for GaAs processes up to 4 GHz, but it can be directly applied to deep submicron CMOS processes as well.