Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45064
DC FieldValueLanguage
dc.contributor.authorShahdadpuri, Mahendraen_US
dc.contributor.authorSosa, J.en_US
dc.contributor.authorNavarro, Héctoren_US
dc.contributor.authorMontiel-Nelson, Juan A.en_US
dc.contributor.authorSarmiento, R.en_US
dc.contributor.otherMontiel-Nelson, Juan-
dc.contributor.otherSarmiento, Roberto-
dc.date.accessioned2018-11-22T06:59:40Z-
dc.date.available2018-11-22T06:59:40Z-
dc.date.issued2003en_US
dc.identifier.isbn0-8194-4977-6en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.urihttp://hdl.handle.net/10553/45064-
dc.description.abstractSystem verification is an important issue to do at every design step to ensure the complete system correctness. The verification effort is becoming more time-consuming due to the increase in design complexity. New environments are necessary to reduce the complexity of this task and most importantly, reduce the time to develop it. Among the languages used in verification, C++ is powerful enough for encapsulating the necessary concepts in a set of classes and templates. This work introduces a framework that allows describing and verifying highly complex systems in a user-friendly and speedy way with C++ classes. These encapsulate hardware description and verification concepts and can be reused throughout a project and also in various development projects. Furthermore, the resulting libraries provide an easy-to-use interface for describing systems and writing test benches in C++, with a transparent connection to an HDL simulator. VESTA includes an advanced memory management with an extremely versatile linked list. The linked list access mode can change on-fly to a FIFO, a LIFO or a memory array access mode, among others. Experimental results demonstrate that the basic types provided by our verification environment excel the features of non-commercial solutions as Openvera or TestBuilder and commercial solutions such as 'e'3 language. Besides, the results achieved have shown significant productivity gain in creating reusable testbenches and in debugging simulation runs.en_US
dc.languageengen_US
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_US
dc.sourceProceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 209-219en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherSimulatorsen_US
dc.subject.otherProcessing timeen_US
dc.titleVESTA: A system level verification environment based on C++en_US
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.typeConferenceObjectes
dc.relation.conferenceConference on VLSI Circuits and Systems
dc.relation.conferenceVLSI Circuits and Systems
dc.identifier.doi10.1117/12.498618
dc.identifier.scopus0041327738-
dc.identifier.isi000183950600021-
dcterms.isPartOfVlsi Circuits And Systems
dcterms.sourceVlsi Circuits And Systems[ISSN 0277-786X],v. 5117, p. 209-219
dc.contributor.authorscopusid6505513329-
dc.contributor.authorscopusid7006310063-
dc.contributor.authorscopusid23028289000-
dc.contributor.authorscopusid6603626866-
dc.contributor.authorscopusid35609452100-
dc.description.lastpage219-
dc.description.firstpage209-
dc.relation.volume5117-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:000183950600021-
dc.contributor.daisngid12250291-
dc.contributor.daisngid1739656
dc.contributor.daisngid27213060-
dc.contributor.daisngid34640290
dc.contributor.daisngid1510114-
dc.contributor.daisngid480589-
dc.contributor.daisngid116294-
dc.identifier.investigatorRIDK-6805-2013-
dc.identifier.investigatorRIDNo ID-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Shahdadpuri, M
dc.contributor.wosstandardWOS:Sosa, J
dc.contributor.wosstandardWOS:Navarro, H
dc.contributor.wosstandardWOS:Montiel-Nelson, JA
dc.contributor.wosstandardWOS:Sarmiento, R
dc.date.coverdateSeptiembre 2003
dc.identifier.conferenceidevents120355
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate19-05-2003-
crisitem.event.eventsstartdate19-05-2003-
crisitem.event.eventsenddate21-05-2003-
crisitem.event.eventsenddate21-05-2003-
crisitem.author.deptGIR IUMA: Instrumentación avanzada-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Instrumentación avanzada-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-1838-3073-
crisitem.author.orcid0000-0003-4323-8097-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSosa González, Carlos Javier-
crisitem.author.fullNameMontiel Nelson, Juan Antonio-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
Appears in Collections:Actas de congresos
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