Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/45001
Campo DC Valoridioma
dc.contributor.authorHernandez, Yerayen_US
dc.contributor.authorLopez, Sebastianen_US
dc.contributor.authorCallico, Gustavo M.en_US
dc.contributor.authorLopez, Jose F.en_US
dc.contributor.authorSarmiento, Robertoen_US
dc.date.accessioned2018-11-22T06:30:30Z-
dc.date.available2018-11-22T06:30:30Z-
dc.date.issued2013en_US
dc.identifier.isbn9791092279016en_US
dc.identifier.issn2164-9766en_US
dc.identifier.urihttp://hdl.handle.net/10553/45001-
dc.description.abstractScalable Video Coding (SVC) is an extension of H.264/AVC standard proposed by Joint Video Team (JVT) to provide flexibility and adaptability on video transmission. For this purpose, this standard exploits the use of layers, what permits to obtain a bit-stream where enhancement layers can be considered to obtain an output video sequence with a higher resolution (temporal or spatial) and/or a higher quality/fidelity. Unfortunately, this versatility comes at the price of an increase in the computational cost of SVC-compliant encoders and decoders, seriously jeopardizing their utilization in applications under tight real-time constraints. To alleviate this problem, this paper proposes a novel inter-layer intra prediction hardware architecture devoted to perform the up-sampling operations in spatially scalable SVC codecs, as this type of scalability has demonstrated to be the most computationally complex of the three types of scalability included in the SVC standard. The proposed architecture has been implemented onto a low-cost FPGA device, being able to process a HDTV 1080p@30fps video sequence at a working frequency as low as 50 MHz. Moreover, as opposed to the static solutions found in the state-of-the-art, the hardware resources of our design can be easily adapted to the processing requirements demanded by the characteristics of the video sequence to be processed, avoiding the waste or the lack of resources in case these requirements become less or more demanding, respectively. These characteristics, together with the utilization of AMBA AXI standard interfaces, definitely convert our architecture into a proper IP module ready to be integrated in a SVC-based video compression system-on-a-chip (SoC).en_US
dc.languageengen_US
dc.relation.ispartofConference on Design and Architectures for Signal and Image Processing, DASIPen_US
dc.sourceConference on Design and Architectures for Signal and Image Processing, DASIP[ISSN 2164-9766] (6661561), p. 312-318en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherStatic VAr compensatorsen_US
dc.subject.otherInterpolationen_US
dc.subject.otherFiltering ,en_US
dc.subject.otherVideo codingen_US
dc.subject.otherScalabilityen_US
dc.titleA novel inter-layer intra prediction architecture for real-time SVC video codecsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.typeConferenceObjectes
dc.relation.conference2013 7th Conference on Design and Architectures for Signal and Image Processing, DASIP 2013
dc.identifier.scopus84892653645-
dc.contributor.authorscopusid57210694283
dc.contributor.authorscopusid8340114700-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid56006321500-
dc.contributor.authorscopusid7404444793-
dc.contributor.authorscopusid35609452100-
dc.description.lastpage318-
dc.identifier.issue6661561-
dc.description.firstpage312-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.date.coverdateDiciembre 2013
dc.identifier.conferenceidevents121496
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.orcid0000-0002-6304-2801-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
crisitem.author.fullNameLópez Feliciano, José Francisco-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
crisitem.event.eventsstartdate08-10-2013-
crisitem.event.eventsenddate10-10-2013-
Colección:Actas de congresos
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