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Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/41297
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dc.contributor.authorMarenzi, Elisaen_US
dc.contributor.authorCarrus, Andreaen_US
dc.contributor.authorDanese, Giovannien_US
dc.contributor.authorLeporati, Francescoen_US
dc.contributor.authorCallico, Gustavo Marreroen_US
dc.date.accessioned2018-06-18T09:25:07Z-
dc.date.available2018-06-18T09:25:07Z-
dc.date.issued2017en_US
dc.identifier.isbn9781509060580
dc.identifier.issn1066-6192en_US
dc.identifier.urihttp://hdl.handle.net/10553/41297-
dc.description.abstractThis paper presents an efficient parallelization of the Motion Estimation procedure, one of the core parts of Super Resolution techniques. The algorithm considered is the basic version of Block Matching Super Resolution, with a single low-resolution camera and fixed Macro Block dimensions. Two are the implementations provided, with OpenMP and in CUDA on an NVIDIA Kepler GPU. Tests have been conducted on five image sequences and the results show a considerable improvement of the CUDA solution in all cases. Consequently, it can be stated that GPUs can efficiently accelerate computational times assuring the same image quality.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017en_US
dc.sourceProceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017 (7912659), p. 274-277en_US
dc.subject330790 Microelectrónicaen_US
dc.subject.otherGPUen_US
dc.subject.otherHigh Performance Computingen_US
dc.subject.otherSuper-Resolutionen_US
dc.titleEfficient parallelization of Motion Estimation for Super-Resolutionen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjectes
dc.relation.conference25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
dc.relation.conference25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017
dc.identifier.doi10.1109/PDP.2017.64
dc.identifier.scopus85019625207
dc.identifier.isi000403395100041-
dc.contributor.authorscopusid55151473500
dc.contributor.authorscopusid57194269626
dc.contributor.authorscopusid6604051702
dc.contributor.authorscopusid55937698500
dc.contributor.authorscopusid56006321500
dc.description.lastpage277-
dc.description.firstpage274-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid5569674
dc.contributor.daisngid28566626
dc.contributor.daisngid30348763
dc.contributor.daisngid797863
dc.contributor.daisngid506422
dc.contributor.wosstandardWOS:Marenzi, E
dc.contributor.wosstandardWOS:Carrus, A
dc.contributor.wosstandardWOS:Danese, G
dc.contributor.wosstandardWOS:Leporati, F
dc.contributor.wosstandardWOS:Callico, GM
dc.date.coverdateAbril 2017
dc.identifier.conferenceidevents121046
dc.identifier.conferenceidevents121603
dc.identifier.ulpgcSíes
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate06-03-2017-
crisitem.event.eventsstartdate06-03-2017-
crisitem.event.eventsenddate08-03-2017-
crisitem.event.eventsenddate08-03-2017-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
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