Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/35729
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lazcano, R. | en_US |
dc.contributor.author | Madroñal, D. | en_US |
dc.contributor.author | Salvador, R. | en_US |
dc.contributor.author | Desnos, K. | en_US |
dc.contributor.author | Pelcat, M. | en_US |
dc.contributor.author | Guerra, R. | en_US |
dc.contributor.author | Fabelo, H. | en_US |
dc.contributor.author | Ortega, S. | en_US |
dc.contributor.author | Lopez, S. | en_US |
dc.contributor.author | Callico, G. M. | en_US |
dc.contributor.author | Juarez, E. | en_US |
dc.contributor.author | Sanz, C. | en_US |
dc.date.accessioned | 2018-05-07T08:15:50Z | - |
dc.date.available | 2018-05-07T08:15:50Z | - |
dc.date.issued | 2017 | en_US |
dc.identifier.issn | 1383-7621 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/35729 | - |
dc.description.abstract | This paper presents a study of the parallelism of a Principal Component Analysis (PCA) algorithm and its adaptation to a manycore MPPA (Massively Parallel Processor Array) architecture, which gathers 256 cores distributed among 16 clusters. This study focuses on porting hyperspectral image processing into many core platforms by optimizing their processing to fulfill real-time constraints, fixed by the image capture rate of the hyperspectral sensor. Real-time is a challenging objective for hyperspectral image processing, as hyperspectral images consist of extremely large volumes of data and this problem is often solved by reducing image size before starting the processing itself. To tackle the challenge, this paper proposes an analysis of the intrinsic parallelism of the different stages of the PCA algorithm with the objective of exploiting the parallelization possibilities offered by an MPPA manycore architecture. Furthermore, the impact on internal communication when increasing the level of parallelism, is also analyzed. Experimenting with medical images obtained from two different surgical use cases, an average speedup of 20 is achieved. Internal communications are shown to rapidly become the bottleneck that reduces the achievable speedup offered by the PCA parallelization. As a result of this study, PCA processing time is reduced to less than 6 s, a time compatible with the targeted brain surgery application requiring 1 frame-per-minute. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Journal of Systems Architecture | en_US |
dc.source | Journal of Systems Architecture[ISSN 1383-7621],v. 77, p. 101-111 | en_US |
dc.subject | 330790 Microelectrónica | en_US |
dc.subject | 220921 Espectroscopia | en_US |
dc.subject.other | Dimensionality reduction | en_US |
dc.subject.other | Hyperspectral imaging | en_US |
dc.subject.other | Massively parallel processing | en_US |
dc.subject.other | Real-time processing | en_US |
dc.title | Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture | en_US |
dc.type | info:eu-repo/semantics/Article | es |
dc.type | info:eu-repo/semantics/Article | en_US |
dc.type | Article | es |
dc.identifier.doi | 10.1016/j.sysarc.2017.05.001 | |
dc.identifier.scopus | 85019908206 | |
dc.identifier.isi | 000404303400010 | - |
dc.contributor.authorscopusid | 57192839213 | |
dc.contributor.authorscopusid | 57192829417 | |
dc.contributor.authorscopusid | 23005852100 | |
dc.contributor.authorscopusid | 55557685700 | |
dc.contributor.authorscopusid | 26435534300 | |
dc.contributor.authorscopusid | 56333613300 | |
dc.contributor.authorscopusid | 56405568500 | |
dc.contributor.authorscopusid | 57189334144 | |
dc.contributor.authorscopusid | 57187722000 | |
dc.contributor.authorscopusid | 56006321500 | |
dc.contributor.authorscopusid | 36447485600 | |
dc.contributor.authorscopusid | 7006751614 | |
dc.identifier.eissn | 1873-6165 | - |
dc.description.lastpage | 111 | - |
dc.description.firstpage | 101 | - |
dc.relation.volume | 77 | - |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Artículo | en_US |
dc.contributor.daisngid | 3634522 | |
dc.contributor.daisngid | 3360488 | |
dc.contributor.daisngid | 1888017 | |
dc.contributor.daisngid | 1853076 | |
dc.contributor.daisngid | 943331 | |
dc.contributor.daisngid | 2216671 | |
dc.contributor.daisngid | 2096372 | |
dc.contributor.daisngid | 1812298 | |
dc.contributor.daisngid | 465777 | |
dc.contributor.daisngid | 506422 | |
dc.contributor.daisngid | 693458 | |
dc.contributor.daisngid | 384271 | |
dc.contributor.wosstandard | WOS:Lazcano, R | |
dc.contributor.wosstandard | WOS:Madronal, D | |
dc.contributor.wosstandard | WOS:Salvador, R | |
dc.contributor.wosstandard | WOS:Desnos, K | |
dc.contributor.wosstandard | WOS:Pelcat, M | |
dc.contributor.wosstandard | WOS:Guerra, R | |
dc.contributor.wosstandard | WOS:Fabelo, H | |
dc.contributor.wosstandard | WOS:Ortega, S | |
dc.contributor.wosstandard | WOS:Lopez, S | |
dc.contributor.wosstandard | WOS:Callico, GM | |
dc.contributor.wosstandard | WOS:Juarez, E | |
dc.contributor.wosstandard | WOS:Sanz, C | |
dc.date.coverdate | Junio 2017 | |
dc.identifier.ulpgc | Sí | es |
dc.description.sjr | 0,255 | |
dc.description.jcr | 0,913 | |
dc.description.sjrq | Q3 | |
dc.description.jcrq | Q3 | |
dc.description.scie | SCIE | |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-4303-3051 | - |
crisitem.author.orcid | 0000-0002-9794-490X | - |
crisitem.author.orcid | 0000-0002-7519-954X | - |
crisitem.author.orcid | 0000-0002-2360-6721 | - |
crisitem.author.orcid | 0000-0002-3784-5504 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Guerra Hernández,Raúl Celestino | - |
crisitem.author.fullName | Fabelo Gómez, Himar Antonio | - |
crisitem.author.fullName | Ortega Sarmiento,Samuel | - |
crisitem.author.fullName | López Suárez, Sebastián Miguel | - |
crisitem.author.fullName | Marrero Callicó, Gustavo Iván | - |
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