Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/35729
DC FieldValueLanguage
dc.contributor.authorLazcano, R.en_US
dc.contributor.authorMadroñal, D.en_US
dc.contributor.authorSalvador, R.en_US
dc.contributor.authorDesnos, K.en_US
dc.contributor.authorPelcat, M.en_US
dc.contributor.authorGuerra, R.en_US
dc.contributor.authorFabelo, H.en_US
dc.contributor.authorOrtega, S.en_US
dc.contributor.authorLopez, S.en_US
dc.contributor.authorCallico, G. M.en_US
dc.contributor.authorJuarez, E.en_US
dc.contributor.authorSanz, C.en_US
dc.date.accessioned2018-05-07T08:15:50Z-
dc.date.available2018-05-07T08:15:50Z-
dc.date.issued2017en_US
dc.identifier.issn1383-7621en_US
dc.identifier.urihttp://hdl.handle.net/10553/35729-
dc.description.abstractThis paper presents a study of the parallelism of a Principal Component Analysis (PCA) algorithm and its adaptation to a manycore MPPA (Massively Parallel Processor Array) architecture, which gathers 256 cores distributed among 16 clusters. This study focuses on porting hyperspectral image processing into many core platforms by optimizing their processing to fulfill real-time constraints, fixed by the image capture rate of the hyperspectral sensor. Real-time is a challenging objective for hyperspectral image processing, as hyperspectral images consist of extremely large volumes of data and this problem is often solved by reducing image size before starting the processing itself. To tackle the challenge, this paper proposes an analysis of the intrinsic parallelism of the different stages of the PCA algorithm with the objective of exploiting the parallelization possibilities offered by an MPPA manycore architecture. Furthermore, the impact on internal communication when increasing the level of parallelism, is also analyzed. Experimenting with medical images obtained from two different surgical use cases, an average speedup of 20 is achieved. Internal communications are shown to rapidly become the bottleneck that reduces the achievable speedup offered by the PCA parallelization. As a result of this study, PCA processing time is reduced to less than 6 s, a time compatible with the targeted brain surgery application requiring 1 frame-per-minute.en_US
dc.languageengen_US
dc.relation.ispartofJournal of Systems Architectureen_US
dc.sourceJournal of Systems Architecture[ISSN 1383-7621],v. 77, p. 101-111en_US
dc.subject330790 Microelectrónicaen_US
dc.subject220921 Espectroscopiaen_US
dc.subject.otherDimensionality reductionen_US
dc.subject.otherHyperspectral imagingen_US
dc.subject.otherMassively parallel processingen_US
dc.subject.otherReal-time processingen_US
dc.titlePorting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architectureen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeinfo:eu-repo/semantics/Articlees
dc.typeArticlees
dc.identifier.doi10.1016/j.sysarc.2017.05.001
dc.identifier.scopus85019908206
dc.identifier.isi000404303400010-
dc.contributor.authorscopusid57192839213
dc.contributor.authorscopusid57192829417
dc.contributor.authorscopusid23005852100
dc.contributor.authorscopusid55557685700
dc.contributor.authorscopusid26435534300
dc.contributor.authorscopusid56333613300
dc.contributor.authorscopusid56405568500
dc.contributor.authorscopusid57189334144
dc.contributor.authorscopusid57187722000
dc.contributor.authorscopusid56006321500
dc.contributor.authorscopusid36447485600
dc.contributor.authorscopusid7006751614
dc.identifier.eissn1873-6165-
dc.description.lastpage111-
dc.description.firstpage101-
dc.relation.volume77-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid3634522
dc.contributor.daisngid3360488
dc.contributor.daisngid1888017
dc.contributor.daisngid1853076
dc.contributor.daisngid943331
dc.contributor.daisngid2216671
dc.contributor.daisngid2096372
dc.contributor.daisngid1812298
dc.contributor.daisngid465777
dc.contributor.daisngid506422
dc.contributor.daisngid693458
dc.contributor.daisngid384271
dc.contributor.wosstandardWOS:Lazcano, R
dc.contributor.wosstandardWOS:Madronal, D
dc.contributor.wosstandardWOS:Salvador, R
dc.contributor.wosstandardWOS:Desnos, K
dc.contributor.wosstandardWOS:Pelcat, M
dc.contributor.wosstandardWOS:Guerra, R
dc.contributor.wosstandardWOS:Fabelo, H
dc.contributor.wosstandardWOS:Ortega, S
dc.contributor.wosstandardWOS:Lopez, S
dc.contributor.wosstandardWOS:Callico, GM
dc.contributor.wosstandardWOS:Juarez, E
dc.contributor.wosstandardWOS:Sanz, C
dc.date.coverdateJunio 2017
dc.identifier.ulpgces
dc.description.sjr0,255
dc.description.jcr0,913
dc.description.sjrqQ3
dc.description.jcrqQ3
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-4303-3051-
crisitem.author.orcid0000-0002-9794-490X-
crisitem.author.orcid0000-0002-7519-954X-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGuerra Hernández, Raúl Celestino-
crisitem.author.fullNameFabelo Gómez, Himar Antonio-
crisitem.author.fullNameOrtega Sarmiento, Samuel-
crisitem.author.fullNameLópez Suárez, Sebastián-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
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