Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/35392
DC FieldValueLanguage
dc.contributor.authorMarenzi, Een_US
dc.contributor.authorTorti, E.en_US
dc.contributor.authorLeporati, F.en_US
dc.contributor.authorQuevedo, Eduardoen_US
dc.contributor.authorMarrero Callicó, Gustavoen_US
dc.date.accessioned2018-04-16T09:21:49Z-
dc.date.available2018-04-16T09:21:49Z-
dc.date.issued2017en_US
dc.identifier.issn0098-3063en_US
dc.identifier.urihttp://hdl.handle.net/10553/35392-
dc.description.abstractThis work presents the computational acceleration of a proprietary Super-Resolution (SR) algorithm (patented) for image and video enhancement. The considered algorithm is based on fusion SR techniques. The version proposed in this paper consists on the comparison of frames divided into Macro Blocks (MB) of fixed dimensions and on acquisition from a single camera. Due to its intensive computation, that limits its practical application in specific contexts where fast processing (even with real-time constraints) is necessary, the algorithm has been implemented in two platforms: OpenMP and GPU. Several tests have been conducted on seven popular image sequences and the results show a considerable improvement of the proposed solutions, in particular the Graphic Processing Units implementations. Consequently, it can be stated that GPUs represent an efficient solution to accelerate this type of algorithms to improve the perception of the image quality.en_US
dc.languageengen_US
dc.relation.ispartofIEEE Transactions on Consumer Electronicsen_US
dc.sourceIEEE Transactions on Consumer Electronics [ISSN 0098-3063], v. 63 (4), p. 368-376, article number 8246793en_US
dc.subject220990 Tratamiento digital. Imágenesen_US
dc.subject.otherImage enhancementen_US
dc.subject.otherMotion estimationen_US
dc.subject.otherParallelizationen_US
dc.subject.otherSuper-Resolutionen_US
dc.titleBlock matching super-resolution parallel GPU implementation for computational imagingen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeinfo:eu-repo/semantics/Articlees
dc.typeArticlees
dc.identifier.doi10.1109/TCE.2017.015077
dc.identifier.scopus85040663915
dc.identifier.isi000423276800004-
dc.contributor.authorscopusid55151473500
dc.contributor.authorscopusid56091390500
dc.contributor.authorscopusid55937698500
dc.contributor.authorscopusid55845740700
dc.contributor.authorscopusid56006321500
dc.identifier.eissn1558-4127-
dc.description.lastpage376-
dc.identifier.issue4-
dc.description.firstpage368-
dc.relation.volume63-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid5569674
dc.contributor.daisngid3356516
dc.contributor.daisngid797863
dc.contributor.daisngid1780822
dc.contributor.daisngid506422
dc.contributor.wosstandardWOS:Marenzi, E
dc.contributor.wosstandardWOS:Torti, E
dc.contributor.wosstandardWOS:Leporati, F
dc.contributor.wosstandardWOS:Quevedo, E
dc.contributor.wosstandardWOS:Callico, GM
dc.date.coverdateNoviembre 2017
dc.identifier.ulpgces
dc.description.sjr0,53
dc.description.jcr1,802
dc.description.sjrqQ1
dc.description.jcrqQ3
dc.description.scieSCIE
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Matemáticas-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-5415-3446-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameQuevedo Gutiérrez, Eduardo Gregorio-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
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