Identificador persistente para citar o vincular este elemento: https://accedacris.ulpgc.es/jspui/handle/10553/157270
Campo DC Valoridioma
dc.contributor.authorLuque, Carlosen_US
dc.contributor.authorMoreto, Miquelen_US
dc.contributor.authorCazorla, Francisco J.en_US
dc.contributor.authorGioiosa, Robertoen_US
dc.contributor.authorBuyuktosunoglu, Alperen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2026-02-06T07:26:02Z-
dc.date.available2026-02-06T07:26:02Z-
dc.date.issued2009en_US
dc.identifier.isbn978-0-7695-3771-9en_US
dc.identifier.issn1089-795Xen_US
dc.identifier.urihttps://accedacris.ulpgc.es/jspui/handle/10553/157270-
dc.description.abstractChip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities when accounting CPU utilization. This is due to the fact that the progress done by an application during an interval of time highly depends on the activity of the other applications it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the application scheduling or the charging mechanism in data centers. We propose a new hardware CPU accounting mechanism to improve the accuracy when measuring the CPU utilization in CMPs and compare it with the previous accounting mechanisms. Our results show that currently known mechanisms lead to a 19% average error when it comes to CPU utilization accounting. Our proposal reduces this error to less than 1% in a modeled 4-core processor system.-
dc.languageengen_US
dc.relation.ispartofInternational Conference on Parallel Architectures and Compilation Techniquesen_US
dc.source18th International Conference on Parallel Architectures and Compilation Techniques [ISBN 978-0-7695-3771-9],p. 203-213 (2009)en_US
dc.subject120317 Informática-
dc.subject.othercache storage-
dc.subject.othermicroprocessor chips-
dc.subject.otherprocessor scheduling-
dc.subject.otherresource allocation-
dc.subject.otherintertask conflict-aware CPU accounting-
dc.subject.otherchip-multiprocessor architecture-
dc.subject.otherinstruction-level parallelism-
dc.subject.otherapplication scheduling-
dc.subject.othercharging mechanism-
dc.subject.otherCPU utilization accounting-
dc.subject.othercache partitioning algorithm-
dc.subject.otherHardware-
dc.subject.otherSwitches-
dc.subject.otherParallel architectures-
dc.subject.otherProposals-
dc.subject.otherPartitioning algorithms-
dc.subject.otherClocks-
dc.subject.otherKernel-
dc.subject.otherLinux-
dc.subject.otherDelay effects-
dc.subject.otherOperating systems-
dc.subject.otherCycle Accounting-
dc.subject.otherChip-MultiProcessor-
dc.subject.otherCache Partitioning Algorithms-
dc.subject.otherFairness-
dc.subject.otherATD-
dc.titleITCA: Inter-task Conflict-Aware CPU Accounting for CMPsen_US
dc.typeconference_paperen_US
dc.relation.conference18th International Conference on Parallel Architectures and Compilation Techniques (PACT 2009)en_US
dc.identifier.doi10.1109/PACT.2009.33en_US
dc.contributor.orcid0000-0003-0442-0785-
dc.description.lastpage213en_US
dc.description.firstpage203en_US
dc.investigacionIngeniería y Arquitectura-
dc.type2Actas de congresosen_US
dc.identifier.external54822334-
dc.description.numberofpages14en_US
dc.utils.revision-
dc.identifier.ulpgcNo-
dc.contributor.buulpgcBU-INFen_US
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0003-0442-0785-
crisitem.author.fullNameRuiz Luque, José Carlos-
crisitem.event.eventsstartdate12-09-2009-
crisitem.event.eventsenddate16-09-2009-
Colección:Actas de congresos
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