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dc.contributor.authorRuiz Luque, José Carlosen_US
dc.date.accessioned2026-02-06T07:26:02Z-
dc.date.available2026-02-06T07:26:02Z-
dc.date.issued2009en_US
dc.identifier.isbn978-0-7695-3771-9en_US
dc.identifier.issn1089-795Xen_US
dc.identifier.urihttps://accedacris.ulpgc.es/jspui/handle/10553/157270-
dc.description.abstractChip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities when accounting CPU utilization. This is due to the fact that the progress done by an application during an interval of time highly depends on the activity of the other applications it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the application scheduling or the charging mechanism in data centers. We propose a new hardware CPU accounting mechanism to improve the accuracy when measuring the CPU utilization in CMPs and compare it with the previous accounting mechanisms. Our results show that currently known mechanisms lead to a 19% average error when it comes to CPU utilization accounting. Our proposal reduces this error to less than 1% in a modeled 4-core processor system.en_US
dc.languageengen_US
dc.relation.ispartofInternational Conference on Parallel Architectures and Compilation Techniquesen_US
dc.source18th International Conference on Parallel Architectures and Compilation Techniques [ISBN 978-0-7695-3771-9],p. 203-213 (2009)en_US
dc.subject120317 Informáticaen_US
dc.subject.othercache storageen_US
dc.subject.othermicroprocessor chipsen_US
dc.subject.otherprocessor schedulingen_US
dc.subject.otherresource allocationen_US
dc.subject.otherintertask conflict-aware CPU accountingen_US
dc.subject.otherchip-multiprocessor architectureen_US
dc.subject.otherinstruction-level parallelismen_US
dc.subject.otherapplication schedulingen_US
dc.subject.othercharging mechanismen_US
dc.subject.otherCPU utilization accountingen_US
dc.subject.othercache partitioning algorithmen_US
dc.subject.otherHardwareen_US
dc.subject.otherSwitchesen_US
dc.subject.otherParallel architecturesen_US
dc.subject.otherProposalsen_US
dc.subject.otherPartitioning algorithmsen_US
dc.subject.otherClocksen_US
dc.subject.otherKernelen_US
dc.subject.otherLinuxen_US
dc.subject.otherDelay effectsen_US
dc.subject.otherOperating systemsen_US
dc.subject.otherCycle Accountingen_US
dc.subject.otherChip-MultiProcessoren_US
dc.subject.otherCache Partitioning Algorithmsen_US
dc.subject.otherFairnessen_US
dc.subject.otherATDen_US
dc.titleITCA: Inter-task Conflict-Aware CPU Accounting for CMPsen_US
dc.typeconference_paperen_US
dc.relation.conference18th International Conference on Parallel Architectures and Compilation Techniques (PACT 2009)en_US
dc.identifier.doi10.1109/PACT.2009.33en_US
dc.contributor.orcid0000-0003-0442-0785-
dc.description.lastpage213en_US
dc.description.firstpage203en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.external54822334-
dc.description.numberofpages14en_US
dc.utils.revisionen_US
dc.identifier.ulpgcNoen_US
dc.contributor.buulpgcBU-INFen_US
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.event.eventsstartdate12-09-2009-
crisitem.event.eventsenddate16-09-2009-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.fullNameRuiz Luque, José Carlos-
Colección:Actas de congresos
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