Identificador persistente para citar o vincular este elemento:
https://accedacris.ulpgc.es/jspui/handle/10553/150228
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Yang, Minzhu | en_US |
dc.contributor.author | Guerra, Raúl | en_US |
dc.contributor.author | Wu, Zhen | en_US |
dc.contributor.author | López, José Fco | en_US |
dc.contributor.author | Han, Changpei | en_US |
dc.contributor.author | Yu, Jiabin | en_US |
dc.date.accessioned | 2025-10-20T12:03:21Z | - |
dc.date.available | 2025-10-20T12:03:21Z | - |
dc.date.issued | 2025 | en_US |
dc.identifier.isbn | 9798331531263 | en_US |
dc.identifier.issn | 2693-2865 | en_US |
dc.identifier.other | Scopus | - |
dc.identifier.uri | https://accedacris.ulpgc.es/jspui/handle/10553/150228 | - |
dc.description.abstract | This paper designs a lossless compression scheme based on interferogram shape for 3D datacubes from the Geostationary Interferometric Infrared Sounder (GIIRS). According to the features of data, this scheme combines Vector Quantization with Linear Prediction to compress. The MATLAB simulations prove that the raised scheme is feasible. Finally, a Xilinx Zynq XC7020 HPSoC is employed to realize this scheme within 1.2508s, achieving compression ratios (CRs) from 3.79 to 3.95. | en_US |
dc.language | eng | en_US |
dc.source | IEEE Joint International Information Technology and Artificial Intelligence Conference (ITAIC)[ISSN 2693-2865], p. 154-158, (Enero 2025) | en_US |
dc.subject | 33 Ciencias tecnológicas | en_US |
dc.subject.other | Cr | en_US |
dc.subject.other | FPGA Implementation | en_US |
dc.subject.other | GIIRS | en_US |
dc.subject.other | Lossless Compression | en_US |
dc.title | A lossless compression method based on vector quantization and linear prediction for 3D GIIRS datacubes | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | 12th IEEE Joint International Information Technology and Artificial Intelligence Conference (ITAIC 2025) | en_US |
dc.identifier.doi | 10.1109/ITAIC64559.2025.11163388 | en_US |
dc.identifier.scopus | 105018212064 | - |
dc.contributor.orcid | NO DATA | - |
dc.contributor.orcid | NO DATA | - |
dc.contributor.orcid | NO DATA | - |
dc.contributor.orcid | NO DATA | - |
dc.contributor.orcid | NO DATA | - |
dc.contributor.orcid | NO DATA | - |
dc.contributor.authorscopusid | 57126569200 | - |
dc.contributor.authorscopusid | 56333613300 | - |
dc.contributor.authorscopusid | 58088139900 | - |
dc.contributor.authorscopusid | 7404444793 | - |
dc.contributor.authorscopusid | 56342154600 | - |
dc.contributor.authorscopusid | 57215546142 | - |
dc.description.lastpage | 158 | en_US |
dc.description.firstpage | 154 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.utils.revision | Sí | en_US |
dc.date.coverdate | Enero 2025 | en_US |
dc.identifier.conferenceid | events156062 | - |
dc.identifier.ulpgc | Sí | en_US |
dc.contributor.buulpgc | BU-TEL | en_US |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-4303-3051 | - |
crisitem.author.orcid | 0000-0002-6304-2801 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Guerra Hernández, Raúl Celestino | - |
crisitem.author.fullName | López Feliciano, José Francisco | - |
crisitem.event.eventsstartdate | 23-05-2025 | - |
crisitem.event.eventsenddate | 25-05-2025 | - |
Colección: | Actas de congresos |
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