A Versatile IP Core for Real-Time Video Compression on Future ESA Missions

Abstract

This paper presents the design, development and implementation of a versatile H264 video encoder IP core tailored for space applications. Given the wide range of space applications — such as Earth Observation, object tracking, and navigation assistance — the developed architecture can be easily customized to their specific requirements. Starting from a base intra-prediction architecture, a variety of options can be added, which include chroma processing, inter-prediction, constant bitrate operational mode, external memory usage and run-time configuration. The IP is capable of autonomously processing video sequences, but an optional coprocessor may also interact with it through standard bus interfaces. The hybrid DSE analyzed the trade-off between performance and complexity in order to optimize the design process and develop an IP that meets the project requirements, and the hierarchical, iterative development process has ultimately resulted in the final design. The synthesis and implementation results have been obtained targeting the Xilinx Kintex Ultrascale KU040 FPGA. These results demonstrate an efficient resource utilization while maintaining robust compression performance when the Intellectual Property (IP) is configured with all the available extensions, while a low-complexity version for resource-constrained applications is also available by selecting the base configuration.