Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/121420
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Benítez Díaz, Domingo Juan | en_US |
| dc.date.accessioned | 2023-03-21T08:17:00Z | - |
| dc.date.available | 2023-03-21T08:17:00Z | - |
| dc.date.issued | 2003 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10553/121420 | - |
| dc.language | spa | en_US |
| dc.subject | 1203 Ciencia de los ordenadores | en_US |
| dc.title | Modelo prestacional para procesadores superescalares con microarquitectura reconfigurable | en_US |
| dc.type | info:eu-repo/semantics/lecture | en_US |
| dc.type | Lecture | en_US |
| dc.relation.conference | XIV Jornadas de Paralelismo Madrid 2003 | en_US |
| dc.investigacion | Ingeniería y Arquitectura | en_US |
| dc.type2 | Artículo | en_US |
| dc.utils.revision | Sí | en_US |
| dc.identifier.ulpgc | Sí | en_US |
| dc.contributor.buulpgc | BU-INF | en_US |
| dc.contributor.buulpgc | BU-INF | en_US |
| dc.contributor.buulpgc | BU-INF | en_US |
| dc.contributor.buulpgc | BU-INF | en_US |
| item.grantfulltext | none | - |
| item.fulltext | Sin texto completo | - |
| crisitem.author.dept | GIR SIANI: Modelización y Simulación Computacional | - |
| crisitem.author.dept | IU Sistemas Inteligentes y Aplicaciones Numéricas | - |
| crisitem.author.dept | Departamento de Informática y Sistemas | - |
| crisitem.author.orcid | 0000-0003-2952-2972 | - |
| crisitem.author.parentorg | IU Sistemas Inteligentes y Aplicaciones Numéricas | - |
| crisitem.author.fullName | Benítez Díaz, Domingo Juan | - |
| Appears in Collections: | Ponencias | |
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