Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/120333
Campo DC Valoridioma
dc.contributor.authorSánchez Clemente, Antonio Joséen_US
dc.contributor.authorBarrios Alfaro,Yubalen_US
dc.contributor.authorVentura Henríquez,Diegoen_US
dc.contributor.authorSarmiento Rodríguez, Robertoen_US
dc.date.accessioned2023-01-30T12:43:13Z-
dc.date.available2023-01-30T12:43:13Z-
dc.date.issued2022en_US
dc.identifier.isbn978-1-6654-7404-7en_US
dc.identifier.issn2771-2508en_US
dc.identifier.urihttp://hdl.handle.net/10553/120333-
dc.description.abstractThe use of third-party IP cores tends to present difficulties because of a lack of standardization in their packaging, distribution and management. Often, IP users find themselves writing code to enable the integration or testing of the IP core, which is not available as part of their distribution. In this work Abeto is presented, a new software tool for IP core databases management. It has been conceived to integrate and use a heterogeneous group of IP cores, described in HDL, with an unified set of instructions. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of common EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate this extent, implementation results for these IP cores on the NanoXplore BRAVE FPGA family are provided, obtained through Abeto.en_US
dc.languageengen_US
dc.relationESA IP Cores Automated Benchmarkingen_US
dc.source25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Spain, 2022en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherDigital systemsen_US
dc.subject.otherEuropean Space Agencyen_US
dc.subject.otherStandardizationen_US
dc.subject.otherPackagingen_US
dc.subject.otherIP networksen_US
dc.subject.otherSoftware toolsen_US
dc.titleAbeto framework: a Solution for Heterogeneous IP Managementen_US
dc.typeinfo:eu-repo/semantics/conferenceobjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference25th Euromicro Conference on Digital System Design (DSD 2022)en_US
dc.identifier.doi10.1109/DSD57027.2022.00101en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.date.coverdateEnero 2023en_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2142-7885-
crisitem.author.orcid0000-0001-6186-9971-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSánchez Clemente, Antonio José-
crisitem.author.fullNameBarrios Alfaro,Yubal-
crisitem.author.fullNameVentura Henríquez,Diego-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
crisitem.project.principalinvestigatorSarmiento Rodríguez, Roberto-
crisitem.event.eventsstartdate31-08-2022-
crisitem.event.eventsenddate02-09-2022-
Colección:Actas de congresos
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