Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/62175
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | López Curbelo, Javier | - |
| dc.contributor.author | Cáceres de León, José Francisco | - |
| dc.date.accessioned | 2020-01-21T09:16:36Z | - |
| dc.date.available | 2007-06-06T00:00:00Z | es |
| dc.date.available | 2020-01-21T09:16:36Z | - |
| dc.date.issued | 1993 | en_US |
| dc.identifier.other | contentdm-postulpgc | es |
| dc.identifier.uri | http://hdl.handle.net/10553/62175 | - |
| dc.format | es | |
| dc.format.mimetype | 300 ppp., TIFF sin compresión | es |
| dc.language | spa | en_US |
| dc.rights | Acceso restringido para la comunidad universitaria de la ULPGC | es |
| dc.subject | 3325 Tecnología de las telecomunicaciones | en_US |
| dc.subject.other | Telecomunicaciones | en_US |
| dc.subject.other | Electrónica | en_US |
| dc.title | Diseño e implementación CMOS ES2 1.5um de la unidad de control de un microprocesador RISC | en_US |
| dc.type | info:eu-repo/semantics/studentThesis | en_US |
| dc.type | StudentThesis | en_US |
| dc.identifier.absysnet | 117461 | es |
| dc.type2 | Proyecto fin de carrera | en_US |
| dc.identifier.currens | 1003 | es |
| dc.description.numberofpages | 222 p. : 8 planos | es |
| dc.utils.revision | Sí | en_US |
| dc.identifier.ulpgc | Sí | es |
| item.fulltext | Con texto completo | - |
| item.grantfulltext | restricted | - |
| Appears in Collections: | Proyecto fin de carrera Restringido ULPGC | |
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