Item View & Download Statistics: Timing analysis for DCFL/SDCFL VLSI circuits

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Region #
NA - North America 39
EU - Europe 21
AS - Asia, other 17
SA - South America 2
Total 79
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Country #
US - United States of America 39
SG - Singapore 13
IE - Ireland 12
HK - Hong Kong 3
AR - Argentina 2
DE - Germany 2
RU - Russian Federation 2
SE - Sweden 2
BE - Belgium 1
FR - France 1
other - Other Country 2
Total 79
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City #
Dublin 12
Singapore 7
Chandler 3
Hong Kong 3
Braunschweig 1
Brussels 1
Chicago 1
Council Bluffs 1
Des Moines 1
Lomas de Zamora 1
other 48
Total 79
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Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Tot
2021 21 0000 0100 01 5
2022 01 0000 1004 37 16
2023 01 1020 0100 01 6
2024 60 1731 4477 00 40
2025 62 1300 0000 00 12
Ever 79