Results 1-20 of 27 (Search time: 0.054 seconds).

Issue DateTitleAuthor(s)Type
12020Neural network training for the detection and classification of oceanic mesoscale eddiesSantana, Oliverio J. ; Hernández-Sosa, Daniel ; Martz, Jeffrey; Smith, Ryan N.Artículoneural_network_training_for_the_detection.pdf.jpg
22014Author retrospective for Software trace cacheRamirez, Alex; Falcón, Ayose J.; Santana, Oliverio J. ; Valero, MateoActas de congresos
32010On the problem of evaluating the performance of multiprogrammed workloadsCazorla, Francisco J.; Pajuelo, Alex; Santana, Oliverio J. ; Fernandez, Enrique; Valero, MateoArtículo
42010Efficient runahead threadsRamirez, Tanausú; Pajuelo, Alex; Santana, Oliverio Jesus ; Mutlu, Onur; Valero, MateoActas de congresos
52009DIA: a complexity-effective decoding architectureSantana, Oliverio J. ; Falcón, Ayose; Ramirez, Alex; Valero, MateoArtículo
62009Code semantic-aware runahead threadsRamírez, Tanauśu; Pajuelo, Alex; Santana, Oliverio J. ; Valero, MateoActas de congresos
72008Runahead threads to improve SMT performanceRamírez, Tanausú; Pajuelo, Alex; Santana, Oliverio J. ; Valero, MateoActas de congresosrunahead_threads_to improve_smt_performance.pdf.jpg
82008LPA: a first approach to the loop processor architectureGarcía, Alejandro; Santana, Oliverio J. ; Fernández, Enrique ; Medina, Pedro ; Valero, MateoActas de congresos
92008Multiple stream predictionSantana, Oliverio J. ; Ramirez, Alex; Valero, MateoActas de congresos
102007Enlarging instruction streamsSantana, Oliverio J. ; Ramirez, Alex; Valero, MateoArtículo
112007FAME: FAirly MEasuring multithreaded architecturesVera, Javier; Cazorla, Francisco J.; Pajuelo, Alex; Santana, Oliverio J. ; Fernández, Enrique, et alActas de congresos
122007Measuring the performance of multithreaded processorsVera, Javier; Cazorla, Francisco J.; Pajuelo, Alex; Santana, Oliverio J. ; Fernandez, Enrique, et alActas de congresos
132007Runahead threads: Reducing resource contention in SMT processorsRamírez, Tanausú; Pajuelo, Alex; Santana, Oliverio J. ; Valero, MateoActas de congresos
142006Kilo-instruction processors, runahead and prefetchingRamírez, Tanausú; Pajuelo González, Alejandro; Santana, Oliverio J. ; Valero Cortés, MateoActas de congresos3686.pdf.jpg
152006Branch predictor guided instruction decodingSantana, Oliverio J. ; Falcón, Ayose; Ramirez, Alex; Valero, MateoActas de congresos
162006A simple speculative load control mechanism for energy savingRamírez, Tanaus; Pajuelo, Alex; Santana, Oliverio J. ; Valero, MateoActas de congresos
172005Kilo-instruction processors: overcoming the memory wallCristal, Adrián; Santana, Oliverio J. ; Cazorla, Francisco; Galluzzi, Marco; Ramírez, Tanausú, et alArtículo
182004A latency-conscious SMT branch prediction architectureFalcón, Ayose; Santana, Oliverio J. ; Ramirez, Alex; Valero, MateoArtículo
192004Toward kilo-instruction processorsCristal, Adrián; Santana, Oliverio J. ; Valero, Mateo; Martínez, José F.Artículo
202004A low-complexity fetch architecture for high-performance superscalar processorsSantana, Oliverio J. ; Ramirez, Alex; Larriba-Pey, Josep L.; Valero, MateoArtículo