Browsing by Author Ramirez, Alex

Showing results 1 to 17 of 17
TitleAuthor(s)???itemlist.dc.contributor.advisor??????itemlist.dc.contributor.editor??????itemlist.dc.contributor.titulacion???Issue Date???itemlist.dc.identifier.doi??????itemlist.dc.source??????itemlist.dc.description.sjr??????itemlist.dc.description.sjrq??????itemlist.dc.description.jcr??????itemlist.dc.description.jcrq???TypePreview
Fetching instruction streamsRamirez, Alex; Santana, Oliverio J. ; Larriba-Pey, Josep L.; Valero, Mateo200210.1109/MICRO.2002.1176264Proceedings of the Annual International Symposium on Microarchitecture, MICRO [ISSN 1072-4451], v. 2002-January (1176264), p. 371-382Actas de congresos
Latency tolerant branch predictorsSantana, Oliverio J. ; Ramirez, Alex; Valero, Mateo200310.1109/IWIA.2003.1262780Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems [ISSN 1537-3223], v. 2003-January (1262780), p. 30-39Actas de congresos
Optimising long-latency-load-aware fetch policies for SMT processorsCazorla, Francisco J.; Ramirez, Alex; Valero, Mateo; Fernandez, Enrique 200410.1504/IJHPCN.2004.009267International Journal of High Performance Computing and Networking [ISSN 1740-0562], v. 2 (1), p. 45-54, (Enero 2004)Artículo
A latency-conscious SMT branch prediction architectureFalcón, Ayose; Santana, Oliverio J. ; Ramirez, Alex; Valero, Mateo200410.1504/IJHPCN.2004.009264International Journal of High Performance Computing and Networking [ISSN 1740-0562], v. 2 (1), p. 11-21Artículo
A low-complexity fetch architecture for high-performance superscalar processorsSantana, Oliverio J. ; Ramirez, Alex; Larriba-Pey, Josep L.; Valero, Mateo200410.1145/1011528.1011532ACM Transactions on Architecture and Code Optimization [ISSN 1544-3566], v. 1 (2), p. 220-245Artículo
Predictable performance in SMT processorsCazorla, Francisco J.; Fernández, Enrique ; Knijnenburg, Peter M.W.; Ramirez, Alex; Sakellariou, Rizos, et al200410.1145/977091.9771522004 Proceedings of the First Computing Frontiers Conference on Computing Frontiers, p. 433-443, (Agosto 2004)Actas de congresos
Reducing fetch architecture complexity using procedure inliningSantana, Oliverio J. ; Ramirez, Alex; Valero, Mateo200410.1109/INTERA.2004.1299514Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004, p. 97-106Actas de congresos
Dynamically controlled resource allocation in SMT processorsCazorla, Francisco J.; Ramirez, Alex; Valero, Mateo; Fernández, Enrique 200410.1109/MICRO.2004.17Proceedings of the Annual International Symposium on Microarchitecture, MICRO, p. 171-182, (Diciembre 2004)Actas de congresos
Implicit vs. explicit resource allocation in SMT processorsCazorla, Francisco J.; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez, Enrique ; Ramirez, Alex, et al200410.1109/DSD.2004.1333257Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004, p. 44-51, (Diciembre 2004)Actas de congresos
Architectural support for real-time task scheduling in SMT processorsCazorla, Francisco J.; Fernández, Enrique ; Knijnenburg, Peter M.W.; Ramirez, Alex; Sakellariou, Rizos, et al200510.1145/1086297.1086320CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, p. 166-176, (Diciembre 2005)Actas de congresos
Predictable performance in SMT processors: synergy between the OS and SMTsCazorla, Francisco J.; Knijnenburg, Peter M. W.; Sakellariou, Rizos; Fernandez, Enrique ; Ramirez, Alex, et al200610.1109/TC.2006.108IEEE Transactions On Computers [ISSN 0018-9340], v. 55 (7), p. 785-799, (Julio 2006)1,426Q1Artículo
Branch predictor guided instruction decodingSantana, Oliverio J. ; Falcón, Ayose; Ramirez, Alex; Valero, Mateo200610.1145/1152154.1152186Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT[ISSN 1089-795X],v. 2006, p. 202-211Actas de congresos
On the problem of minimizing workload execution time in SMT processorsCazorla, Francisco J.; Fernández, Enrique ; Knijnenburg, Peter M.W.; Ramirez, Alex; Sakellariou, Rizos, et al200710.1109/ICSAMOS.2007.4285735Proceedings - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007, p. 66-73, (Diciembre 2007)Actas de congresos
Enlarging instruction streamsSantana, Oliverio J. ; Ramirez, Alex; Valero, Mateo200710.1109/TC.2007.70742IEEE Transactions on Computers[ISSN 0018-9340],v. 56, p. 1342-13571,68Q1Artículo
Multiple stream predictionSantana, Oliverio J. ; Ramirez, Alex; Valero, Mateo2008Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)[ISSN 0302-9743],v. 4759 LNCS, p. 1-16Actas de congresos
DIA: a complexity-effective decoding architectureSantana, Oliverio J. ; Falcón, Ayose; Ramirez, Alex; Valero, Mateo200910.1109/TC.2008.170IEEE Transactions on Computers [ISSN 0018-9340], v. 58, p. 448-4621,822Q1Artículo
Author retrospective for Software trace cacheRamirez, Alex; Falcón, Ayose J.; Santana, Oliverio J. ; Valero, Mateo201410.1145/2591635.2594508Proceedings of the International Conference on Supercomputing, p. 45-47Actas de congresos