Browsing by Author Arteaga, R.

Showing results 1 to 7 of 7
Issue DateTitleAuthor(s)TypePreview
2003A practical high-level methodology case study: Implementation of an ATM over SDH transceiver from the system specificationArteaga, R.; Tobajas, F. ; Esper-Chain, R. ; De Armas Sosa, Valentín ; Sarmiento, R. Actas de congresos
2004Split-engine packet classification: A novel approach to multi-field packet classification on high performance routers with QoS SupportTobajas, F. ; Cañero, V.; De Armas Sosa, Valentín ; Esper-Chaín, R. ; Arteaga, R., et alActas de congresos
2005A Gigabit Multidrop Serial Backplane for High-Speed Digital Systems Based on Asymmetrical Power SplitterEsper-Chaín, R. ; Tobajas, F. ; Tubío, O.; Arteaga, R.; De Armas Sosa, Valentín , et alArtículo
2005A novel gigabit multidrop serial link for high-speed digital systemsTobajas, F. ; Esper-Chain, R. ; Arteaga, R.; Santana, O.; De Armas Sosa, Valentín , et alActas de congresos
2007Variable length packet scheduler algorithm with QoS supportArteaga, R.; Tobajas, F. ; Esper-Chaín, R. ; Monzón, M. A.; Regidor, R., et alActas de congresos
2008GMDS: Hardware implementation of novel real output queuing architectureArteaga, R.; Tobajas, F. ; Esper-Chain, R. ; De Armas Sosa, Valentín ; Sarmiento, Roberto Actas de congresos
2009Hardware implementation of a scheduler for high performance switches with Quality of Service supportArteaga, R.; Tobajas, F. ; De Armas Sosa, Valentín ; Sarmiento, R. Actas de congresosHardware_implementation_of_a_scheduler_for_high_pe.pdf.jpg