Browsing by Author Abbott, D.

Showing results 1 to 8 of 8
TitleAuthor(s)???itemlist.dc.contributor.advisor??????itemlist.dc.contributor.editor??????itemlist.dc.contributor.titulacion???Issue Date???itemlist.dc.identifier.doi??????itemlist.dc.source??????itemlist.dc.description.sjr??????itemlist.dc.description.sjrq??????itemlist.dc.description.jcr??????itemlist.dc.description.jcrq???TypePreview
GaAs asynchronous morphological processor for interactive mobile telemedicineNooshabadi, S.; Abbott, D.; Eshraghian, K.; Montiel-Nelson, J. A. 1997Proceedings of the Australian Microelectronics Conference, p. 29-33Actas de congresos
GaAs pseudodynamic latched logic for high performance processor coresLópez, J. F. ; Eshraghian, K.; Sarmiento, R. ; Núnez, A. ; Abbott, D.199710.1109/4.604094IEEE Journal of Solid-State Circuits[ISSN 0018-9200],v. 32, p. 1297-13030,922Q1Artículo
Neu-MOS (νMOS) for smart sensors and extension to a novel neu-GaAs (νGaAs) paradigmAbbott, D.; Al-Sarawi, S. F.; Gonzalez, B. ; Lopez, J. ; Austin-Crowe, J., et al1998Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems,v. 3, p. 397-404Artículo79bb9254cf0154e151ed4a0ac61ee96151ef.pdf.jpg
Low power techniques for digital GaAs VLSILopez, J. F. ; Sarmiento, R. ; Nunez, A. ; Eshraghian, K.; Lachowicz, S., et al1999Proceedings of the IEEE Great Lakes Symposium on VLSI[ISSN 1066-1395], p. 321-324Actas de congresos
Complementary neu-GaAs structureCelinski, P.; López, J. F. ; Al-Sarawi, S.; Abbott, D.200010.1049/el:20000384Electronics Letters[ISSN 0013-5194],v. 36, p. 424-4250,931Q2Artículo
Novel extension of neu-MOS techniques to neu-GaAsCelinski, P.; Abbott, D.; Al-Sarawi, S. F.; López, J. F. 2000Microelectronics Journal[ISSN 0026-2692],v. 31, p. 577-5820,608Q2Artículo
Low power, high speed, charge recycling CMOS threshold logic gateCelinski, P.; López, J. F. ; Al-Sarawi, S.; Abbott, D.200110.1049/el:20010742Electronics Letters[ISSN 0013-5194],v. 37, p. 1067-10690,97Q2Artículo
Compact parallel (m,n) counters based on self-timed threshold logicCelinski, P.; López, J. F. ; Al-Sarawi, S.; Abbott, D.200210.1049/el:20020438Electronics Letters[ISSN 0013-5194],v. 38, p. 633-6351,542Q1Artículo