accedaCRIShttps://accedacris.ulpgc.es/jspuiThe accedaCRIS digital repository system captures, stores, indexes, preserves, and distributes digital research material.Sun, 03 Nov 2024 22:36:14 GMT2024-11-03T22:36:14Z5021An intrinsic order criterion to evaluate, large, complex fault treeshttp://hdl.handle.net/10553/72709Title: An intrinsic order criterion to evaluate, large, complex fault trees
Authors: González, L.; García, D.; Galván, B.
Abstract: A new efficient algorithm is introduced to evaluate (non) coherent fault trees, obtaining exact lower & upper bounds on system unavailability, with a prespecified maximum error. The algorithm is based on the canonical normal form of the Boolean function, but overcomes the large number of terms needed, by using an intrinsic order criterion (IOC) to select the elementary states to evaluate. This intrinsic order implies lexicographic (truth table) order. The criterion guarantees a priori that the probability of a given elementary system state is always greater than or equal to the probability of another state, for any set of basic probabilities. IOC is exclusively based on the positions of 0 & 1 in the binary n-tuples defining the elementary states. The algorithm does not require any qualitative analysis of the fault tree. The computational cost mainly depends on the basic event probabilities, and is related to system complexity, only because the Boolean function must be evaluated.
Thu, 01 Jan 2004 00:00:00 GMThttp://hdl.handle.net/10553/727092004-01-01T00:00:00ZError Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approacheshttp://hdl.handle.net/10553/112928Title: Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches
Authors: Sánchez Clemente, Antonio José; Entrena, Luis; Hrbacek, Radek; Sekanina, Lukas
Abstract: Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.
Fri, 01 Jan 2016 00:00:00 GMThttp://hdl.handle.net/10553/1129282016-01-01T00:00:00Z